Browse tech roles

Filter the feed by workplace, employment type, salary floor, and post age. For ranked matching against your resume, use AI Match.

Active Keyword: DFT Remove filter Clear all

11 of up to 20 (filtered)

DFT Engineer - New College Grad

Nvidia

Santa Clara, CA 23 days ago $116,000–$189,750
Actively hiring Competitive pay
Perl Python Tcl DFT BIST ATPG fault simulation RTL design STA place-n-route power analysis Silicon debug ATE pattern formats failure processing test program development
Save

CPU DFT Engineer

Qualcomm

Santa Clara, CA 27 days ago $142,200–$213,400
Actively hiring Competitive pay
Verilog VHDL Mentor Tessent tools TCL Perl Python Shell scripting JTAG ATPG IEEE 1500 Standard MBIST LBIST SOC level verification Test compression software
Save

ASIC Technical Leader- DFT

Cisco

Remote (San Jose, CA) 29 days ago $183,800–$263,600
Actively hiring Above market
Tcl Python Perl Verilog TestMax Tetramax Tessent JTAG ATPG PostgreSQL Git CI/CD Docker Kubernetes AWS GCP Azure SVN Mercurial
Remote
Save

ASIC DFT CAD Technical Leader

Cisco

Remote (San Jose, CA) 30 days ago $183,800–$263,600
Actively hiring Above market
Tcl Python Perl shell scripting EDA DFT toolchain Synopsys TestMAX Synopsys VCS Siemens Tessent LSF AI/ML techniques data analytics tools pandas dashboards visualization tools large-scale regression systems distributed job management STIL
Remote
Save

ASIC Engineering Technical Lead - DFT

Cisco

San Jose, CA 36 days ago $183,800–$263,600
Actively hiring Above market
Python Tcl C++ Siemens_Tessent Synopsys RTL Verilog System_Verilog DFT ATPG SDF Scan_Insertion Memory_BIST Logic_BIST ATE_testers
Save

ASIC DFT Technical Lead

Cisco

Remote (San Jose, CA) 43 days ago $210,600–$305,100
Actively hiring Above market
Tcl Python Perl Jtag Scan BIST Memory BIST Boundary Scan RTL Lint CDC Post-silicon test bring up Debugging Silicon validation Yield support DFT DFx In-system test Debug and diagnostics
Remote
Save

ASIC Technical Lead- DFT

Cisco

Remote (San Jose, CA) 50 days ago $210,600–$305,100
Actively hiring Above market
Jtag Scan BIST ATPG TestMax Tetramax Tessent PrimeTime SystemVerilog Verilog Python Perl Makefile Git CI/CD PostgreSQL Docker Kubernetes
Remote
Save

ASIC Engineering Technical Leader - DFT

Cisco

Remote (San Jose, CA) 63 days ago $183,800–$263,600
Actively hiring Above market
Jtag Scan BIST ATPG TestMax Tetramax Tessent PrimeTime VCS Gate level simulation P1687 Verilog System Verilog Logic Equivalency checking DFT CAD development Test Static Timing Analysis
Remote
Save

ASIC Engineering Technical Leader- DFT

Cisco

Remote (San Jose, CA) 84 days ago $210,600–$305,100
Actively hiring Above market
Jtag Scan BIST ATPG TestMax Tetramax Tessent PrimeTime VCS Gate level simulation P1687 Verilog System Verilog Logic Equivalency checking DFT CAD development Test Static Timing Analysis Post-silicon validation
Remote
Save

Senior DFT Engineer

Nvidia

Santa Clara, CA 90 days ago $168,000–$264,500
Actively hiring Above market
DFT ATPG EDA VLSI ATE Python AI CI/CD Kubernetes AWS Git Jenkins PostgreSQL Mentoring 2.5D_IC 3D_IC Multi-Chiplet_Architecture
Hybrid
Save

Senior Engineer - Design for Test (DFT) | Microsoft Careers

Microsoft

US 156 days ago $119,800–$234,700
Actively hiring Verified listing Above market
Verilog System Verilog Mentor Tessent Synopsys TestMax Tcl Perl AI ATE Static Timing Analysis Gate-level Simulation Coverage Analysis Waveform Debugging RTL Quality Assurance JTAG Memory BIST Scan Architecture EDA Tools Silicon Bring-up Yield & Diagnosis
Save