Physical Design

Qualcomm

Confirmed live today Trusted

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$121,800–$182,600 / yr
Posted
25 days ago
Freshness
Confirmed live today
Closes
Mar 31, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $205k
This role $152k
$105k $275k
below market most similar roles pay here above market

This role pays less than 89% of similar roles. Most pay $172,000–$238,787 — the blue band above. At the midpoint, this role pays about $152k versus about $205k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

Most-posted roles

View all roles at Qualcomm

At a glance

TL;DR · Physical Design

Role Posting Log in to save

Physical Design (Multiple levels) engineers join the ASICS Engineering team to develop leading-edge products on advanced process technologies. This role involves executing the full physical design flow from synthesized netlist to tape-out for complex, high-speed, and low-power ASICs and SoCs. Key responsibilities include floorplanning, partitioning, power planning, IR-drop analysis, placement, clock tree synthesis, routing, and timing closure across Multi-Mode Multi-Corner scenarios. Engineers must resolve timing violations, signal integrity issues, and crosstalk effects while performing RC extraction and physical verification. The role requires proficiency with Cadence Innovus, Synopsys Fusion Compiler, and Synopsys PrimeTime SI. Candidates should possess skills in Python, Perl, TCL, Shell scripting, and C/C++ within Linux/Unix environments to develop automation tools and innovative low-power implementation methodologies for high-performance computing and mobile products.

Skills

ASIC Design Physical Design Cadence Innovus Synopsys Fusion Compiler Synopsys PrimeTime SI Python TCL Perl C/C++ Shell Scripting Static Timing Analysis Clock Tree Synthesis DFT Formal Verification RC Extraction IR-drop Analysis Linux Unix

What you'll do

  • Execute all stages of the physical design flow from synthesized netlist to tape-out.
  • Perform floorplanning, partitioning, power planning, and IR-drop analysis for complex ASICs and SoCs.
  • Execute placement, clock tree synthesis, routing, and timing optimization across MMMC scenarios.
  • Analyze and resolve timing violations, signal integrity issues, crosstalk, and physical design rule violations.
  • Perform RC extraction, physical verification, and formal verification activities.
  • Implement engineering change orders and support design convergence through sign-off.
  • Develop automation and productivity tools using scripting languages like Python, Perl, and TCL.

What we're looking for

  • Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
  • Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
  • PhD in Science, Engineering, or related field.
  • 2-10+ years of industry experience or relevant academic/project experience in Physical Design.
  • Experience in ASIC/SoC Physical Design implementation (preferred).
  • Experience with Place and Route using Cadence Innovus and/or Synopsys Fusion Compiler (preferred).
  • Experience with Static Timing Analysis and timing closure using Synopsys PrimeTime SI (preferred).
  • Programming and automation skills using Python, Perl, TCL, Shell scripting, C/C++, and Linux/Unix environments (preferred).

Related searches

More Physical Design jobs Physical Design jobs in San Diego All jobs at Qualcomm

More like this

Similar roles

Physical Design Engineer

Qualcomm

San Diego, CA +2 40 days ago $123,100–$250,000
ASIC Design Physical Design Place and Route Static Timing Analysis Clock Tree Synthesis Floorplanning Power Planning Signal Integrity Analysis Physical Verification DFT Low Power Design UPF Python Tcl Perl Shell Linux Unix Cadence Innovus Synopsys Fusion Compiler Synopsys PrimeTime RC Extraction ECO Implementation
4+ yrs exp
Save

Physical Design Engineer

Qualcomm

San Diego, CA 8 days ago $174,400–$261,600
ASIC SoC Physical Design Cadence Innovus Synopsys Fusion Compiler Synopsys PrimeTime SI Python Perl TCL C/C++ Shell Scripting Linux Unix Static Timing Analysis Clock Tree Synthesis DFT Formal Verification RC Extraction IR-drop Analysis
10+ yrs exp
Save

Infra Systems Physical Architect

Qualcomm

San Diego, CA 40 days ago $145,600–$218,400
ASIC Design NoC Physical Design Python TCL Perl C Linux Unix Shell AMBA Protocol Design Compiler Fusion Compiler Genus Primetime Prime power Innovus DFT Formal Verification Signal Integrity
6+ yrs exp
Save

Physical Design/Implementation Engineer, Staff

Qualcomm

Austin, TX 40 days ago $145,600–$218,400
ASIC Design Physical Design Synthesis PnR Static Timing Analysis STA Clock Tree Synthesis CTS Floorplanning Routing UPF low-power design Python Tcl Fusion Compiler Genus Innovus ICC2 PrimeTime Tempus LEC Version Control Configuration Management Regression
4+ yrs exp
Save

Physical Design Methodology CAD Engineer

Apple Inc

Santa Clara, CA 40 days ago $184,700–$324,800
Physical Design CAD Flow Tcl Python Perl PNR Static Timing Analysis STA RC Extraction Physical Verification EMIR ML GenAI SoC Design
10+ yrs exp
Save