Physical Design

Qualcomm

Confirmed live yesterday Trusted

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $115,600–$173,400 / yr
Posted: 29 days ago
Freshness: Confirmed live yesterday
Closes: Feb 9, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $196k

This role $144k

$100k most similar roles pay here $257k

This role pays less than 87% of similar roles. Most pay $170,000–$221,550 — the shaded band above. At the midpoint, this role pays about $144k versus about $196k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · Physical Design

Role Posting Log in to save

Physical Design (Multiple levels) engineers join the SoC and ASIC Design organization to develop high-performance computing, AI, mobile, automotive, and data center products using advanced process technologies. The role involves executing the full physical design flow from synthesized netlist to tape-out for complex, high-speed, and low-power ASICs and SoCs. Key responsibilities include floorplanning, partitioning, power planning, IR-drop analysis, clock tree synthesis, routing, timing optimization, and signal integrity resolution. Candidates will perform RC extraction, physical verification, and implement engineering change orders while developing automation tools. Required skills include proficiency in Cadence Innovus, Synopsys Fusion Compiler, and Synopsys PrimeTime SI. The role also requires expertise in low-power design methodologies and programming using Python, Perl, TCL, Shell scripting, C/C++, and Linux/Unix environments to solve critical hardware implementation challenges across various multi-mode multi-corner scenarios.

Skills

Physical Design ASIC SoC Cadence Innovus Synopsys Fusion Compiler Synopsys PrimeTime SI Python TCL Perl C/C++ Shell Scripting Linux Unix Clock Tree Synthesis Static Timing Analysis RC Extraction DFT Signal Integrity Floorplanning Routing

What you'll do

Execute the full physical design flow from synthesized netlist to tape-out.
Develop physical design solutions for high-speed and low-power ASICs and SoCs.
Perform floorplanning, partitioning, power planning, and IR-drop analysis.
Execute placement, clock tree synthesis, routing, and timing closure across MMMC scenarios.
Resolve timing violations, signal integrity issues, crosstalk effects, and physical design rule violations.
Conduct RC extraction, physical verification, and formal verification activities.
Implement engineering change orders (ECOs) to support design convergence through sign-off.
Develop automation and productivity tools using scripting languages like Python, Perl, and TCL.

What we're looking for

Bachelor's degree in Science, Engineering, or a related field with 2+ years of ASIC design experience.
Master's degree in Science, Engineering, or a related field with 1+ year of ASIC design experience.
PhD in Science, Engineering, or a related field.
2 to 10+ years of industry experience or relevant academic/project experience in Physical Design.
Experience in ASIC/SoC Physical Design implementation (preferred).
Proficiency in Place and Route using Cadence Innovus or Synopsys Fusion Compiler (preferred).
Experience with Static Timing Analysis, physical verification, and low-power design methodologies (preferred).
Programming skills in Python, Perl, TCL, Shell scripting, C/C++, and Linux/Unix environments (preferred).

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