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Verilog SystemVerilog UVM Python Perl Veloce Palladium Zebu HAPS PCIe Ethernet RDMA TCP Fiber Channel Formal verification iEV/vc formal Jasper Gold AI agents Cursor Codex CoPilot Forwarding logic Parsers P4 +19 more Show less

Calibre ICV Pegasus Python TCL Makefile DRC LVS ESD PERC CI/CD +6 more Show less

Calibre ICV Pegasus Python TCL Makefile DRC LVS ESD PERC CI/CD +6 more Show less

Calibre ICV Pegasus Python TCL Makefile DRC LVS ESD PERC CI/CD +6 more Show less

Python CI/CD

Python CI/CD

Python CI/CD

Python CI/CD

Python ASIC verification FPGA verification

Python CI/CD

Python ASIC verification FPGA verification

Python CI/CD

Python ASIC verification FPGA design Test bench development Digital ASIC verification System level testing Code coverage Functional coverage CI/CD +4 more Show less

UVM Python

UVM Python

UVM Python

UVM Python

Python C++ C# CI/CD Cloud-native architectures Generative AI Machine Learning Docker +3 more Show less

SystemVerilog UVM Linux C C++ Python Perl Veloce Palladium Zebu HAPS Networking Dashboard_management CI/CD +9 more Show less

SystemVerilog UVM Linux C++ Python Perl Veloce Palladium Zebu HAPS CI/CD Networking Dashboard_management Emulation_platforms +9 more Show less