Design Verification Engineering Lead - Silicon One

Cisco

Remote

Quick summary

Work type: Remote
Location: San Jose, CA
Salary: $210,600–$305,100 / yr
Posted: 7 days ago
Closes: Aug 25, 2026
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $191k

This role $258k

$123k most similar roles pay here $325k

This role pays more than 96% of similar roles. Most pay $165,200–$216,250 — the shaded band above. At the midpoint, this role pays about $258k versus about $191k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 167 open roles on FindRole.

Listed pay typically runs $168,800–$241,400 across 167 roles with salary data.

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At a glance

TL;DR · Design Verification Engineering Lead - Silicon One

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Join Cisco’s dynamic team as an ASIC Design Verification Engineer and contribute to the development of cutting-edge data center solutions by architecting DV infrastructure from scratch for complex chips, ensuring comprehensive verification coverage, and collaborating closely with designers and software teams. You will maintain existing DV environments, support tests during emulation, debug issues found in firmware development, and be responsible for ASIC bring-up. Ideal candidates have extensive experience with Verilog, SystemVerilog, UVM, scripting languages like Perl or Python, and formal verification tools such as Jasper Gold. Knowledge of protocols including PCIe, Ethernet, RDMA, TCP, and Fiber Channel is highly valued, along with familiarity with AI agents and forwarding logic/Parsers/P4. This role offers a unique blend of startup culture and the resources of a leading networking company, focusing on innovative chip design for large-scale systems integration.

Skills

Verilog SystemVerilog UVM Python Perl Veloce Palladium Zebu HAPS PCIe Ethernet RDMA TCP Fiber Channel Formal verification iEV/vc formal Jasper Gold AI agents Cursor Codex CoPilot Forwarding logic Parsers P4

What you'll do

Architect and develop DV infrastructure for block, cluster, and top-level environments.
Create comprehensive test plans to ensure robust verification and coverage of complex chips.
Collaborate with ASIC designers to maintain and enhance existing DV environments.
Support firmware development by debugging issues found during software testing phases.
Responsible for bringing up new ASICs and ensuring their seamless integration into systems.

What we're looking for

Extensive experience in ASIC design and verification processes.
Proficiency in Verilog, SystemVerilog, and UVM within the last 2-3 years.
Strong scripting skills with Perl or Python.
Experience verifying blocks/clusters or full chip level for ASICs.
Knowledge of Veloce/Palladium/Zebu/HAPS emulation tools.
Expertise in one or more protocols like PCIe, Ethernet, RDMA, TCP, FC.

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