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Verilog SysVerilog C++ Python Perl TCL AgenticAI ClaudeCode Cursor CoPilot EDA ASIC Design for Testing Scan ATPG JTAG +11 more Show less

SystemVerilog UVM SVA Git Linux Python Tcl Makefile DO-254 SVUnit Formal verification CDC verification Ethernet PCIe MIL-STD-1553 SPI CI/CD Nix +13 more Show less

SystemVerilog UVM Formal Verification Low-Power Verification PCIe CPU Multi-processor systems Power Management DMA DDR USB PLL UPF Python CI/CD +10 more Show less

SystemVerilog UVM Formal Verification Low-Power Verification PCIe CPU DMA DDR USB PLL UPF Python CI/CD +8 more Show less

SystemVerilog UVM Formal Verification Low-Power Verification PCIe CPU Multi-processor systems Power Management DMA DDR USB PLL UPF Python CI/CD +10 more Show less

SystemVerilog UVM SystemC C++ Python Perl LLMs MCPs SVA Coverage_driven_verification CI/CD +6 more Show less

SystemVerilog UVM SystemC C++ Python Perl DV Methodologies LLMs MCPs Constraint Random Testing SVA Coverage Driven Verification +7 more Show less

SystemVerilog C++ Python Perl UVM Verilog VHDL Hierarchical design Top-down design SoC verification CI/CD +6 more Show less

C C++ Java Ada GitLab Bitbucket JIRA Confluence DO-178B/C CI/CD Python PostgreSQL Kubernetes AWS Docker +10 more Show less

C++ SystemVerilog UVM VCS Debussy GDB Python CI/CD Random Stimulus Functional Coverage Assertion-Based Verification Object Oriented Programming +7 more Show less

SystemVerilog JasperGold VC Formal Python AI tools CI/CD SystemVerilog Assertions GPU architecture LPU architecture Formal Verification Mentor Graphics Calibre Cadence Incisive Veriflow +7 more Show less

SystemVerilog UVM Perl Python dc_shell VCS Debussy GDB CI/CD ASIC RTL Object-Oriented Programming +7 more Show less

UVM SystemVerilog Python Coherent Hub Interface (CHI) PCIe CXL Universal Verification Methodology (UVM) System Verilog Test Bench (SVTB) generative AI Virtualization Security Interrupts Protocol Bridges +8 more Show less

Python GoogleTest CI/CD Agile DevSecOps Terraform AWS Kubernetes PostgreSQL Docker Prometheus Grafana +7 more Show less

SystemVerilog Python UVM SVTB TDD Mentorship Verification_IP JEDEC_spec Generative_AI CI/CD EDA_tools DIMM_VIP Coverage_driven_verification Random_stimulus_techniques +9 more Show less

UVM System Verilog Python Coherent Hub Interface (CHI) cache coherency architectures Universal Verification Methodology (UVM) System Verilog Test Bench (SVTB) generative AI C++ Perl Tcl +6 more Show less

SystemVerilog UVM C C++ EDA tools Regression automation Job farm management ASIC/SoC functional verification Project risk identification Verification sign-off Coverage closure methodologies Tape-out achievements Multi-functional project leadership +8 more Show less

Python C++ Git JIRA Confluence CI/CD JUnit PostgreSQL AWS Kubernetes Docker Terraform Prometheus Grafana Earned Value Management(EVM) +10 more Show less

SystemVerilog UVM Python Perl C++ VHDL Verilog SystemC AI ML GenAI 4G/5G 3GPP Formal Verification Simulation Acceleration Unix/Linux Makefiles XML OOP HW/SW Co-Verification +15 more Show less

Python JavaScript PowerShell .Net Azure DevOps Agile CI/CD +2 more Show less