Senior DDR IP Verification Engineer | Microsoft Careers

Microsoft

Quick summary

Work type
On-site
Location
—
Salary
$119,800–$234,700 / yr
Posted
3 days ago
Closes
Nov 29, 2026

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Competitive pay

How this pay compares to similar roles

Similar $181k
This role $177k
$106k most similar roles pay here $248k

This role pays more than 54% of similar roles. Most pay $152,760–$209,050 — the shaded band above. At the midpoint, this role pays about $177k versus about $181k for comparable roles.

Based on 240 similar postings.

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About Microsoft

Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing

Microsoft currently has 728 open roles on FindRole.

Listed pay typically runs $119,800–$234,700 across 664 roles with salary data.

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TL;DR · Senior DDR IP Verification Engineer | Microsoft Careers

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The DDR IP DV Individual Contributor Engineer position at the Compute Silicon & Manufacturing Engineering team involves leading or owning verification of memory controller Intellectual Property (IP) and DDR subsystem integration with Physical Layer (PHY). This role requires defining verification strategies, developing environments, running simulations, and applying random-stimulus techniques to ensure high-quality designs. The engineer will also innovate by improving verification efficiency through methodologies or tools and utilize generative AI solutions for daily tasks. Key skills include experience in pre-silicon subsystem/IP verification, DDR subsystem verification, and a deep understanding of JEDEC specifications. Preferred qualifications involve expertise with UVM, System Verilog Test Bench (SVTB), Python scripting, and full product cycle verification from definition to silicon delivery.

Skills

SystemVerilog Python UVM SVTB TDD Mentorship Verification_IP JEDEC_spec Generative_AI CI/CD EDA_tools DIMM_VIP Coverage_driven_verification Random_stimulus_techniques

What you'll do

  • Own or lead verification of memory controller IP and DDR subsystem integration.
  • Define verification strategies and test plans in collaboration with partner teams.
  • Develop verification environments and run simulations to drive quality improvements.
  • Apply random-stimulus and coverage-based techniques to identify bugs effectively.
  • Innovate methodologies or tools to enhance verification efficiency continuously.
  • Coach and mentor team members on verification expertise and best practices.

What we're looking for

  • 7+ years of related technical engineering experience or equivalent education/experience combination.
  • 5+ years of pre-silicon subsystem or IP verification experience.
  • 3+ years of DDR subsystem verification experience.
  • Experience verifying memory controller, DDR PHY, and integration with EDA vendor VIP.
  • Deep understanding of JEDEC spec including mode registers, timing parameters, refresh operations, initialization, calibration, training, power management, and error handling.
  • Ability to create, maintain, or integrate test benches using UVM, SVTB, and Python for post-processing checking.

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