Design Verification Engineer

Apple Inc

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Work type: On-site
Location: Austin, TX
Posted: 136 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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How this pay compares to similar roles

Similar $200k

$141k $242k

below market most similar roles pay here above market

This listing doesn't post a salary. Most similar roles pay $169,625–$230,087.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · Design Verification Engineer

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The Design Verification Engineer joins the silicon design group to ensure the quality and reliability of next-generation cellular systems, specifically high-throughput cellular baseband modems and transceiver link controllers. The role involves crafting highly reusable UVM verification environments, developing comprehensive coverage-driven and directed test cases, and architecting test benches with stimulus, checkers, and reference models. Key responsibilities include constructing detailed test plans, implementing RTL simulation bring-up to sign-off, and maintaining regressions. The position requires proficiency in System Verilog, UVM, System C, C/C++, and Python/perl. Candidates must possess skills in constraint random testing, SVA, and LLM-based workflows to improve productivity. The work focuses on complex IP and subsystem architectures, including 4G/5G cellular physical layer operations, advanced fabric protocols, and low-power architectures.

What does a Design Verification Engineer earn?

Median $189224 from 84 postings across 10 companies.

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Skills

UVM System Verilog Python C++ System C Perl Coverage Driven Verification SVA Constraint Random Testing LLM ML RTL Simulation AXI AHB NoC 3GPP 4G 5G

What you'll do

Construct detailed test plans for design components including specific use cases.
Create and refine coverage-driven verification plans from technical specifications.
Architect reusable UVM-based test benches with stimulus, checkers, VIPs, and reference models.
Design and implement ML-driven workflows to increase verification productivity and quality.
Execute test plans from RTL simulation bring-up to final sign-off.
Report and debug verification failures throughout the design cycle.
Maintain regressions and report progress against test plans and coverage metrics.

What we're looking for

BS degree and a minimum of 10 years of relevant industry experience.
Strong knowledge of System Verilog and UVM.
Skilled in System C, C/C++, and Python/perl.
Highly proficient in developing and establishing DV Methodologies.
Experience in using LLMs and MCPs.
Experience with developing Python-based automation solutions.
Experience with constraint random testing, SVA, and coverage-driven verification.
Master of Science degree in Electrical Engineering/Computer Science (preferred).