Design Verification Engineer

Apple Inc

Quick summary

Work type: On-site
Location: Austin, TX
Posted: 4 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

How this pay compares to similar roles

Similar $183k

$126k most similar roles pay here $230k

This listing doesn't post a salary. Most similar roles pay $155,272–$209,750.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1777 open roles on FindRole.

Listed pay typically runs $162,500–$272,100 across 1443 roles with salary data.

Most-posted roles

View all roles at Apple Inc

At a glance

TL;DR · Design Verification Engineer

Apply Now Log in to save

Senior Verification Engineer position available in the Hardware Development team at Alibaba Cloud. This role involves developing and implementing DV methodologies for complex hardware systems, utilizing System Verilog, UVM, and Python-based automation solutions. Day-to-day responsibilities include creating test plans, conducting constraint random testing, and leveraging SVA and coverage-driven verification techniques to ensure high-quality products. Candidates should be proficient in System C, C/C++, and scripting languages like Python and Perl, with a focus on enhancing efficiency through the use of LLMs and MCPs. This role addresses critical business needs by ensuring robust verification processes for large-scale hardware projects at Alibaba Cloud.

Skills

SystemVerilog UVM SystemC C++ Python Perl DV Methodologies LLMs MCPs Constraint Random Testing SVA Coverage Driven Verification

What you'll do

Develop and establish DV methodologies for hardware verification.
Write System Verilog and UVM tests for complex systems.
Create Python-based automation solutions to enhance verification processes.
Utilize constraint random testing, SVA, and coverage-driven techniques.
Plan and execute comprehensive test strategies with strong problem-solving skills.
Leverage LLMs and MCPs to improve the efficiency of verification tasks.

What we're looking for

Proficient in System Verilog, UVM, and Python for developing DV methodologies.
Skilled in C/C++, SystemC, and constraint random testing with SVA coverage.
Experience in developing Python-based automation solutions and using LLMs/MCPs.
Strong test planning and problem-solving abilities required.
Familiarity with verification improvement through the use of LLMs preferred.

Save