Design Verification Engineer

Apple Inc

Confirmed live 2 days ago Low trust

Quick summary

Work type
On-site
Location
Austin, TX
Posted
91 days ago
Freshness
Confirmed live 2 days ago
Nearby
99+ roles within 25 mi

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Salary context

How this pay compares to similar roles

Similar $188k
$126k most similar roles pay here $230k

This listing doesn't post a salary. Most similar roles pay $159,562–$216,062.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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At a glance

TL;DR · Design Verification Engineer

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As a Design Verification Engineer, you will join the silicon design group to ensure the quality and reliability of next-generation cellular systems. You will be responsible for crafting highly reusable UVM verification environments, developing coverage-driven and directed test cases, and constructing detailed test plans for complex IP and subsystem designs. Your daily work involves building test benches with stimulus, checkers, and reference models while implementing test plans from RTL simulation bring-up to sign-off. The role requires expertise in SystemVerilog, UVM, SystemC, C/C++, Python, Perl, SVA, and constraint random testing. You will also utilize LLMs and ML-driven workflows to enhance verification efficiency. This position focuses on the technical challenges of high-throughput cellular baseband modems and transceiver link controllers, specifically addressing complex IP architectures, advanced fabric protocols, and 4G/5G cellular physical layer operations.

Skills

UVM System Verilog Python C++ System C SVA coverage driven verification Constraint Random Testing LLM Prompt Engineering RTL Simulation 4G 5G 3GPP AXI AHB NoC Bus Fabric Automation

What you'll do

  • Construct detailed test plans including specific use cases for various design components.
  • Create and refine coverage-driven verification plans based on technical specifications.
  • Architect reusable UVM-based test benches featuring stimulus, checkers, VIPs, and reference models.
  • Implement test plans from initial RTL simulation bring-up through final sign-off.
  • Identify, report, and debug failures during the verification process.
  • Maintain regression suites and track progress against coverage metrics.
  • Integrate LLMs and ML-driven workflows to improve verification efficiency and quality.

What we're looking for

  • Bachelor of Science degree and at least 10 years of relevant industry experience.
  • Master of Science degree in Electrical Engineering or Computer Science is preferred.
  • Strong knowledge of System Verilog and UVM methodologies.
  • Proficiency in System C, C/C++, Python, and Perl.
  • Experience with constraint random testing, SVA, and coverage-driven verification.
  • Experience using LLMs and MCPs to enhance verification processes and workflows.
  • Experience developing Python-based automation solutions.
  • Knowledge of 4G/5G cellular physical layer operation (3GPP) and bus architectures like AXI or AHB is preferred.

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