Wireless SOC Verification Engineer

Apple Inc

Quick summary

Work type: On-site
Location: Irvine, CA
Salary: $120,300–$210,100 / yr
Posted: 4 days ago
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $187k

This role $165k

$108k most similar roles pay here $233k

This role pays less than 64% of similar roles. Most pay $165,200–$209,112 — the shaded band above. At the midpoint, this role pays about $165k versus about $187k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1777 open roles on FindRole.

Listed pay typically runs $162,500–$272,100 across 1443 roles with salary data.

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At a glance

TL;DR · Wireless SOC Verification Engineer

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As a Wireless SOC Verification Engineer at Apple, you will join the cutting-edge Wireless SOC team to verify complex system-on-chip designs for the latest iPhones. Your daily tasks include crafting and integrating UVM-based testbenches, delivering targeted coverage, and collaborating with design, architecture, software, firmware, and external IP teams to ensure high-quality tape-out readiness. You will work on advanced features such as power management schemes, low-power methodologies, and multi-chip SOC debug architectures, requiring expertise in SystemVerilog, UVM methodology, and formal verification. This role demands a deep understanding of high-efficiency SOC architecture, standard peripherals, and complex protocols like PCIe, USB, and DDR, enabling you to contribute to the development of state-of-the-art wireless systems at scale.

Skills

SystemVerilog UVM Formal Verification Low-Power Verification PCIe CPU Multi-processor systems Power Management DMA DDR USB PLL UPF Python CI/CD

What you'll do

Understand complex SOC architectures including peripherals like PCIE, CPUs, and low-power schemes.
Design and deliver power management solutions using UPF simulations for efficient power up-down scenarios.
Architect UVM-based testbenches to integrate multi-instance VIPs and subsystem test suites at the SOC level.
Achieve targeted verification coverage by collaborating with design, architecture, SW, FW, and external IP teams.
Work with DV methodology architects to enhance verification metrics and methodologies.

What we're looking for

Extensive experience in RTL verification of complex SOCs
Proficiency in SystemVerilog, Verilog, and UVM methodology
Hands-on expertise in designing highly reusable UVM testbenches
Strong background in low-power design and verification methodologies
Experience with formal verification techniques and tools
Knowledge of SOC peripherals including PCIe, CPUs, and multi-processor systems

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