Wireless SOC Verification Engineer

Apple Inc

Quick summary

Work type: On-site
Location: Sunnyvale, CA
Salary: $126,800–$220,900 / yr
Posted: 4 days ago
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $187k

This role $174k

$116k most similar roles pay here $232k

This role pays more than 51% of similar roles. Most pay $165,200–$209,112 — the shaded band above. At the midpoint, this role pays about $174k versus about $187k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1777 open roles on FindRole.

Listed pay typically runs $162,500–$272,100 across 1443 roles with salary data.

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At a glance

TL;DR · Wireless SOC Verification Engineer

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As a Design Verification Engineer at Apple, you will join the Wireless SOC team to verify complex systems on chips (SOCs) for cutting-edge iPhones. Your daily tasks include crafting and integrating UVM-based testbenches, delivering targeted coverage, and collaborating with design, architecture, software, firmware, and external IP teams to ensure high-quality tape-out readiness. You will work on advanced features such as power management schemes, low-power methodologies, and multi-chip SOC debug architectures, using SystemVerilog and UVM methodology extensively. This role requires expertise in high-efficiency SOC architecture, standard peripherals like PCIe and CPUs, and a deep understanding of wireless protocols and firmware-hardware interactions. With opportunities to innovate and improve the product experience globally, this position is ideal for those passionate about pushing the boundaries of wireless technology at scale.

Skills

SystemVerilog UVM Formal Verification Low-Power Verification PCIe CPU Multi-processor systems Power Management DMA DDR USB PLL UPF Python CI/CD

What you'll do

Understand complex SOC architectures including peripherals like PCIE, CPUs, and power management schemes.
Design and deliver low-power methodologies for Power Management using UPF simulations.
Architect UVM-based testbenches to integrate multi-instance VIPs and subsystem test suites at the SOC level.
Achieve targeted verification coverage by collaborating with design, architecture, SW, FW teams and external IP providers.
Work with DV methodology architects to enhance verification metrics and processes.

What we're looking for

Extensive experience in RTL verification of complex SOCs.
Proficiency in System Verilog, Verilog, and UVM methodology.
Expertise in designing and integrating UVM-based testbenches.
Hands-on experience with low-power design methodologies and UPF simulations.
Familiarity with formal verification techniques for hardware designs.
Knowledge of high-efficiency SOC architecture and standard peripherals.

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