Wireless SOC Verification Engineer

Apple Inc

Confirmed live today Low trust

Quick summary

Work type: On-site
Location: Sunnyvale, CA
Salary: $129,300–$225,300 / yr
Posted: 137 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $205k

This role $177k

$116k $255k

below market most similar roles pay here above market

This role pays less than 57% of similar roles. Most pay $168,500–$241,750 — the blue band above. At the midpoint, this role pays about $177k versus about $205k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · Wireless SOC Verification Engineer

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The Wireless SOC Verification Engineer joins the Wireless SOC team to verify complex, high-efficiency silicon designs for wireless and Bluetooth chips. The role involves pre-silicon RTL verification of block and top-level SOC components, focusing on high-speed layered protocols and low-power architectures. Key responsibilities include creating coverage-driven verification plans from specifications, architecting reusable UVM testbenches, and integrating multi-instance VIPs and sub-system test suites. The engineer will work on power management designs using UPF simulations and verify peripherals like PCIe, CPUs, DMA, DDR, and USB. Required technical skills include SystemVerilog, Verilog, and UVM methodology. The position addresses technical challenges in multi-chip SOC debug architecture, FW-HW interactions, and achieving tape-out readiness for sophisticated wireless systems within a multi-functional silicon design group.

Skills

SystemVerilog UVM Verilog ASIC SOC Formal Verification UPF RTL Verification PCIe DDR DMA USB Power Management Low Power Verification Coverage Driven Verification Multi-processor Systems Memory Controller Subsystems

What you'll do

Perform pre-silicon RTL verification for block and top-level SOC designs.
Architect highly reusable UVM-based test benches and integrate complex multi-instance VIPs.
Create and refine coverage-driven verification plans based on technical specifications.
Deliver power management designs using low-power methodologies and UPF simulations.
Implement coverage-driven and directed test cases to achieve specific coverage targets.
Integrate and verify overall SOC designs with design, architecture, software, and firmware teams.
Work with DV methodology architects to improve and refine verification metrics.

What we're looking for

Bachelor’s degree is required.
Experience with SystemVerilog, Verilog, or UVM is required.
Strong problem solving and analytical skills are required.
Expertise in SystemVerilog coding and UVM methodology (preferred).
Dedicated or hands-on ASIC and SOC DV experience (preferred).
Experience with Formal Verification (preferred).
Low Power Verification experience (preferred).

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