SoC Verification Lead

What you'll do

• Own the SoC-level verification plan, schedule, and achievement tracking from project conception through tape-out.
• Serve as the primary Person-in-Charge (PIC) across all verification workstreams for AI-enabled SoC designs.
• Coordinate with architects, IP owners, and infrastructure engineers to align on coverage goals and resolve bottlenecks.
• Lead risk identification and mitigation planning throughout the entire verification lifecycle.
• Track open issues across multiple teams and report risks to project leadership with clear mitigation plans.
• Define and evolve SoC verification flows and methodologies to meet next-generation chip complexity requirements.
• Partner with tape-out teams to define and close verification sign-off criteria at each milestone.

What we're looking for

• Bachelor’s degree or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 15+ years of hands-on experience in ASIC/SoC functional verification.
• Deep understanding of SoC-level verification challenges and flows from block integration to tape-out sign-off.
• Proven track record leading or coordinating verification efforts across multiple IPs and multi-functional teams.
• Proficiency in SystemVerilog and UVM-based testbench development.
• Familiarity with C/C++ for directed and hardware-controlled test development at the SoC level.
• Solid grasp of verification infrastructure, including EDA tool configuration, regression automation, and job farm management.
• Demonstrated experience in project risk identification, tracking, and mitigation.