Senior Verification Engineer, Hardware

Nvidia

Confirmed live yesterday Trusted

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$168,000–$264,500 / yr
Posted
91 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $188k
This role $216k
$129k most similar roles pay here $279k

This role pays more than 83% of similar roles. Most pay $166,538–$208,900 — the shaded band above. At the midpoint, this role pays about $216k versus about $188k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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At a glance

TL;DR · Senior Verification Engineer, Hardware

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The Senior Verification Engineer - Hardware joins the Emulation division to support multiple emulation environments using advanced techniques including C/C++ DPI Transactors, SV assertions, Coverage, Power Estimation, SpeedBridges, and Accelerated UVM Testbenches. This role involves bringing up SOCs on emulation, root causing SoC or Processor test failures, and resolving emulator environment issues through collaboration with Design, DV, Power, Silicon Validation, Performance, and Software teams. The candidate will also lead emulation vendors to debug issues using various tools. Required technical skills include proficiency in Verilog, VHDL, C/C++, and SystemVerilog, along with experience in UVM verification environments and scripting with Perl, Python, and C++. The role requires expertise in hierarchical design approach, top-down design, and SoC and system level verification to solve complex hardware problems within the emulation domain.

Skills

SystemVerilog UVM C C++ Verilog VHDL Python Perl Emulation Power Estimation SpeedBridges DPI Transactors Coverage

What you'll do

  • Support multiple emulation environments using C/C++ DPI Transactors, SV assertions, and Accelerated UVM Testbenches.
  • Bring up SoCs on emulation platforms to ensure proper functionality.
  • Root cause SoC and processor test failures within the emulator environment.
  • Identify and resolve technical issues within the emulation infrastructure.
  • Lead emulation vendors in debugging issues using a variety of specialized tools.
  • Perform system-level verification for complex SoC designs.
  • Develop scripts using Perl, Python, or C/C++ to support verification workflows.

What we're looking for

  • Master's degree or equivalent experience in Electrical Engineering, Computer Science, Computer Engineering, or a related field.
  • At least 3 years of proven experience in the field.
  • Proficiency in Verilog and/or VHDL, C/C++, and SystemVerilog.
  • Experience with UVM verification environments is essential.
  • Proficiency in scripting with Perl, Python, and C/C++ is required.
  • Familiarity with hierarchical design approach, top-down design, and SoC or system level verification.

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