Senior Verification Engineer - Hardware

Nvidia

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $168,000–$264,500 / yr
Posted: 4 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $193k

This role $216k

$130k most similar roles pay here $279k

This role pays more than 82% of similar roles. Most pay $169,100–$216,250 — the shaded band above. At the midpoint, this role pays about $216k versus about $193k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 980 open roles on FindRole.

Listed pay typically runs $168,000–$270,250 across 966 roles with salary data.

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At a glance

TL;DR · Senior Verification Engineer - Hardware

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NVIDIA seeks a Senior Verification Engineer to join its esteemed Emulation division in Santa Clara, CA. In this role, you will support multiple emulation environments using advanced techniques such as C/C++ DPI Transactors and SystemVerilog assertions, while also bringing up SOCs on emulation platforms and resolving test failures and environment issues. You will collaborate closely with Design, DV, Power, Silicon Validation, Performance, and Software teams to ensure seamless integration and functionality of complex systems. Proficiency in Verilog or VHDL, along with expertise in C/C++ and SystemVerilog, is essential, as is experience with UVM verification environments and scripting languages like Perl, Python, and C++. Familiarity with hierarchical design approaches and SoC-level verification is also required for this challenging yet rewarding position.

Skills

SystemVerilog C++ Python Perl UVM Verilog VHDL Hierarchical design Top-down design SoC verification CI/CD

What you'll do

Support multiple emulation environments using advanced techniques like DPI transactors and SV assertions.
Root cause SOC/Processor test failures and resolve emulator environment issues.
Collaborate with cross-functional teams including Design, DV, Power, Silicon Validation, Performance, and Software.
Lead emulation vendors in debugging issues through various tools and methodologies.
Develop accelerated UVM testbenches for efficient verification processes.

What we're looking for

M.S. or equivalent experience in Electrical Engineering, Computer Science, or related field.
3+ years of proven experience in emulation environments.
Proficient in Verilog/VHDL, C/C++, and SystemVerilog.
Experience with UVM verification environments and scripting in Perl, Python, and C/C++.
Familiarity with hierarchical design approach, top-down design, SoC, and system level verification.

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