Wireless SOC Verification Engineer

Apple Inc

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $120,300–$210,100 / yr
Posted: 4 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $187k

This role $165k

$108k most similar roles pay here $233k

This role pays less than 64% of similar roles. Most pay $165,200–$209,112 — the shaded band above. At the midpoint, this role pays about $165k versus about $187k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1777 open roles on FindRole.

Listed pay typically runs $162,500–$272,100 across 1443 roles with salary data.

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At a glance

TL;DR · Wireless SOC Verification Engineer

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As a Wireless SOC Verification Engineer at Apple, you will join the cutting-edge Wireless SOC team to verify complex system-on-chip designs for next-generation iPhones. Your daily responsibilities include understanding high-efficiency SOC architecture and integrating multiple IP-level DV environments, crafting UVM testbenches, and implementing coverage-driven tests. You will work closely with design, architecture, software, firmware, and external IP teams to ensure the successful integration and verification of the entire SOC design. This role requires expertise in SystemVerilog and UVM methodology, as well as experience in formal verification and low-power verification techniques. The team focuses on pushing industry boundaries by improving wireless protocol chip requirements and enhancing product experiences for global customers.

Skills

SystemVerilog UVM Formal Verification Low-Power Verification PCIe CPU DMA DDR USB PLL UPF Python CI/CD

What you'll do

Understand complex SOC architectures including peripherals like PCIe, CPUs, and power management schemes.
Design and deliver low-power methodologies for power up-down scenarios using UPF simulations.
Architect UVM-based testbenches to integrate multi-instance VIPs and subsystem test suites at the SOC level.
Achieve targeted coverage by collaborating with design, architecture, SW, FW, and external IP teams.
Work with DV methodology architects to enhance verification metrics and improve overall SOC design quality.

What we're looking for

Extensive experience in RTL verification of complex SOCs.
Proficiency in SystemVerilog, Verilog, and UVM methodology.
Expertise in designing highly reusable UVM testbenches.
Hands-on experience with low-power design methodologies.
Knowledge of formal verification techniques and tools.
Collaborative work with cross-functional teams on SOC projects.

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