Senior Design Verification Engineer | Microsoft Careers

Microsoft

Quick summary

Work type
On-site
Location
US
Salary
$119,800–$234,700 / yr
Posted
3 days ago
Closes
Nov 29, 2026

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $189k
This role $177k
$106k most similar roles pay here $248k

This role pays more than 64% of similar roles. Most pay $162,748–$216,250 — the shaded band above. At the midpoint, this role pays about $177k versus about $189k for comparable roles.

Based on 240 similar postings.

Employer

About Microsoft

Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing

Microsoft currently has 728 open roles on FindRole.

Listed pay typically runs $119,800–$234,700 across 664 roles with salary data.

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At a glance

TL;DR · Senior Design Verification Engineer | Microsoft Careers

The Senior Design Verification Engineer role within the Verification & Validation team focuses on enhancing Microsoft’s cloud hardware manufacturing processes by defining and implementing operational measures for quality, delivery, and sustainability. This engineer will own or lead verification of complex flows at either the Fabric Interconnect level or block level, developing UVM-based verification environments to drive quality through random-stimulus and coverage-based techniques. Key responsibilities include innovating methodologies and tools to improve verification efficiency, applying generative AI solutions, and mentoring team members. The ideal candidate has 5+ years of pre-silicon subsystem or IP verification experience with a focus on CHI and AMBA protocols, along with hands-on technical leadership skills in creating schedules, coordinating work across teams, and integrating test benches using UVM, SVTB, and Python for post-processing checks.

What you'll do

  • Own or lead verification of complex flows at Fabric Interconnect or block level.
  • Develop UVM-based verification environments and run simulations to drive quality improvements.
  • Apply random-stimulus and coverage-based techniques to identify bugs and meet test plan goals.
  • Innovate methodologies or tools to enhance verification efficiency and effectiveness.
  • Coach and mentor team members in verification strategies and best practices.

What we're looking for

  • 5+ years of pre-silicon subsystem or IP verification experience.
  • Expertise in verifying designs using CHI and AMBA protocols.
  • Experience with fabric interconnects, coherency, virtualization, security, PCIe, CXL, and protocol bridges.
  • Proven ability to drive IP verification through full product cycles from definition to silicon.
  • Hands-on technical leadership in creating schedules, coordinating work, and solving cross-team problems.
  • Proficiency in UVM, SVTB, and Python for test bench creation and maintenance.
  • Experience applying generative AI solutions to daily tasks.

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