Design Verification Engineer

Apple Inc

Confirmed live yesterday Low trust

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Work type: On-site
Location: Austin, TX
Posted: 136 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

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How this pay compares to similar roles

Similar $200k

$141k $242k

below market most similar roles pay here above market

This listing doesn't post a salary. Most similar roles pay $169,625–$230,087.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · Design Verification Engineer

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The Design Verification Engineer joins the silicon design group to ensure the quality and reliability of next-generation cellular systems. This role focuses on verifying high-throughput cellular baseband modems and transceiver link controllers for SOCs. The engineer will architect reusable UVM verification environments, develop coverage-driven and directed test cases, and implement test plans from RTL simulation bring-up to sign-off. Key responsibilities include constructing detailed test plans, maintaining regressions, and debugging failures. Required technical skills include System Verilog, UVM, System C, C/C++, and Python/perl. Candidates must understand constraint random testing, SVA, and coverage-driven verification. The role also involves leveraging Large Language Models and ML-driven workflows to improve productivity. Domain expertise includes 4G/5G cellular physical layer operations, bus architectures like AXI and AHB, and low-power architectures.

What does a Design Verification Engineer earn?

Median $189224 from 84 postings across 10 companies.

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Skills

UVM System Verilog Python C++ System C Perl Coverage Driven Verification SVA LLM ML 4G 5G 3GPP AXI AHB NOC Bus Fabric RTL Simulation

What you'll do

Construct detailed test plans for design components including specific use cases.
Create and refine coverage-driven verification plans from technical specifications.
Architect reusable UVM-based test benches with stimulus, checkers, and reference models.
Design and implement ML-driven workflows to increase verification productivity and quality.
Execute test plans from RTL simulation bring-up through to final sign-off.
Report and debug verification failures throughout the design cycle.
Maintain regressions and report progress against test plans and coverage metrics.

What we're looking for

Knowledge of System Verilog and UVM.
Experience with System C, C/C++, and Python/Perl.
Ability to develop and establish DV Methodologies.
Ability to use LLMs and MCPs.
Ability to develop Python-based automation solutions.
Understanding of constraint random testing, SVA, and coverage-driven verification.
Master of Science degree in Electrical Engineering/Computer Science (preferred).
Bachelor's degree.

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