Design Verification Engineer

Apple Inc

Quick summary

Work type
On-site
Location
Austin, TX
Posted
3 days ago

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How this pay compares to similar roles

Similar $183k
$126k most similar roles pay here $230k

This listing doesn't post a salary. Most similar roles pay $156,000–$209,750.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1777 open roles on FindRole.

Listed pay typically runs $162,500–$272,100 across 1443 roles with salary data.

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At a glance

TL;DR · Design Verification Engineer

As a Senior Verification Engineer joining our dynamic hardware development team, you will play a pivotal role in ensuring the reliability and robustness of complex systems through comprehensive validation. Your daily tasks will include developing and implementing DV methodologies, leveraging System Verilog, UVM, and Python for automation solutions, while also utilizing LLMs to enhance verification processes. You will be responsible for test planning, constraint random testing, and coverage-driven verification, ensuring thorough analysis with SVA. This role requires a strong background in C/C++, Python, and Perl, alongside expertise in SystemC and UVM. Ideal candidates possess deep knowledge of hardware verification techniques and the ability to solve intricate problems efficiently within our large-scale semiconductor product development environment.

What you'll do

  • Develop and implement DV methodologies for hardware verification.
  • Use System Verilog and UVM for developing verification environments.
  • Create Python-based automation solutions to enhance testing processes.
  • Apply constraint random testing, SVA, and coverage-driven verification techniques.
  • Plan tests and solve problems effectively in the verification phase.

What we're looking for

  • Bachelor's degree required.
  • Proficiency in System Verilog, UVM, and Python scripting.
  • Experience with C/C++, SystemC, and developing DV methodologies.
  • Ability to use LLMs and MCPs for verification tasks.
  • Expertise in constraint random testing, SVA, and coverage-driven verification.

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