Design Verification Engineer

Apple Inc

Confirmed live 2 days ago Low trust

Quick summary

Work type: On-site
Location: Austin, TX
Posted: 91 days ago
Freshness: Confirmed live 2 days ago
Nearby: 99+ roles within 25 mi

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Salary context

How this pay compares to similar roles

Similar $188k

$126k most similar roles pay here $230k

This listing doesn't post a salary. Most similar roles pay $159,562–$216,062.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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At a glance

TL;DR · Design Verification Engineer

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As a Design Verification Engineer, you will join the silicon design group to ensure the quality and reliability of next-generation cellular systems, specifically focusing on high-throughput cellular baseband modems and transceiver link controllers for SoCs. You will be responsible for constructing detailed test plans, creating coverage-driven verification plans from specifications, and architecting reusable UVM-based test benches featuring stimulus, checkers, VIPs, and reference models. Your daily work involves implementing test plans from RTL simulation bring-up to sign-off while managing regressions and reporting progress against coverage metrics. You will utilize SystemVerilog, UVM, SystemC, C/C++, Python, Perl, and SVA to validate complex IP and subsystem designs. Additionally, you will leverage Large Language Models and ML-driven workflows to enhance verification efficiency across advanced fabric protocols, 4G/5G cellular physical layer operations, and low-power architectures.

Skills

UVM System Verilog Python C++ SVA coverage driven verification LLM RTL Simulation 3GPP AXI AHB NoC Perl Constraint Random Testing Firmware

What you'll do

Construct detailed test plans including specific use cases for various design components.
Create and refine coverage-driven verification plans based on technical specifications.
Architect reusable UVM-based test benches featuring stimulus, checkers, VIPs, and reference models.
Integrate Large Language Models (LLMs) to enhance verification efficiency and quality.
Design and implement ML-driven workflows to increase team productivity.
Execute test plans from RTL simulation bring-up through final sign-off while debugging failures.
Maintain regression suites and report progress against coverage metrics.

What we're looking for

Minimum requirement of a bachelor's degree.
Master of Science degree in Electrical Engineering or Computer Science is preferred.
Knowledge of System Verilog and UVM.
Experience with System C, C/C++, Python, and Perl.
Ability to develop and establish Design Verification (DV) methodologies.
Ability to use LLMs, MCPs, and prompt engineering for verification workflow optimization.
Ability to develop Python-based automation solutions.
Understanding of constraint random testing, SVA, coverage-driven verification, and 4G/5G cellular physical layer operation.

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