Physical Design Engineer, Silicon Engineering

SpaceX

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Work type
On-site
Location
Austin, TX
Posted
3 days ago
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Confirmed live today
Nearby
99+ roles within 25 mi

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Similar $196k
$142k most similar roles pay here $255k

This listing doesn't post a salary. Most similar roles pay $164,687–$227,500.

Based on 240 similar postings.

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About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 689 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 450 roles with salary data.

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TL;DR · Physical Design Engineer, Silicon Engineering

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Physical Design Engineer (Silicon Engineering) joins a cross-disciplinary team to develop next-generation ASICs for space and ground infrastructure. This role focuses on creating hardware that enables global connectivity through the Starlink network. Day-to-day responsibilities include performing partition synthesis, floorplanning, power/ground grid generation, place and route, and various signoff checks such as static timing analysis, noise, physical verification, electromigration, and voltage drop. The engineer will also develop automation scripts and collaborate with the ASIC design team on architectural feasibility studies and RTL trade-offs. Required skills include experience in RTL2GDSII flow development, knowledge of FinFET and CMOS solid state physics, and proficiency in scripting languages like Python, Perl, TCL, or Bash. Candidates should be familiar with industry standard EDA tools and understand DFT, Scan, MBIST, and LBIST impacts on physical design flows.

Skills

ASIC Physical Design RTL2GDSII Static Timing Analysis STA EDA Tools Python TCL Perl Bash Makefile FinFET CMOS DFT Scan MBIST LBIST Floorplanning Place and Route Physical Verification

What you'll do

  • Perform partition synthesis and physical implementation steps including floorplanning, power/ground grid generation, and place and route.
  • Execute signoff checks for timing, noise, physical verification, electromigration, voltage drop, and logic equivalency.
  • Develop and improve physical design methodologies and automation scripts for various implementation steps.
  • Conduct architectural feasibility studies with the ASIC design team to establish timing, power, and area targets.
  • Resolve complex design, timing, and congestion issues while identifying and driving technical solutions.
  • Debug and fix signoff closure issues in static timing analysis and other physical verification flows.

What we're looking for

  • Bachelor's degree in electrical engineering, computer engineering, or computer science.
  • 1+ years of professional experience working on RTL2GDSII physical design and/or physical design flow development.
  • Must be a U.S. citizen, national, lawful permanent resident, refugee, or asylee (or eligible for such status) to meet ITAR requirements.
  • Experience with industry standard EDA tools including understanding of their capabilities and underlying algorithms (preferred).
  • Knowledge of deep sub-micron FinFET and CMOS solid state physics (preferred).
  • Understanding of CMOS digital design principles, standard cell functionality, and power dissipation in deep submicron processes (preferred).
  • Familiarity with CMOS analog circuit and physical design (preferred).
  • Good scripting skills in csh/bash, Perl, Python, TCL, or Makefile (preferred).

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