Physical Design Engineer, Silicon Engineering

SpaceX

Confirmed live today High trust

Quick summary

Work type
On-site
Location
Palo Alto, CA
Salary
$135,000–$175,000 / yr
Posted
3 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $197k
This role $155k
$122k most similar roles pay here $258k

This role pays less than 82% of similar roles. Most pay $167,462–$227,500 — the shaded band above. At the midpoint, this role pays about $155k versus about $197k for comparable roles.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 689 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 450 roles with salary data.

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View all roles at SpaceX

At a glance

TL;DR · Physical Design Engineer, Silicon Engineering

Role Posting Log in to save

As a Physical Design Engineer (Silicon Engineering), you will join a cross-disciplinary team to develop next-generation ASICs for space and ground infrastructure. You will perform critical physical implementation steps including partition synthesis, floorplanning, power/ground grid generation, place and route, and various signoff checks such as static timing analysis, noise, electromigration, and voltage drop. The role involves developing automation scripts and collaborating with the ASIC design team to drive architectural feasibility studies and resolve congestion issues. You will utilize industry-standard EDA tools while applying knowledge of deep sub-micron FinFET and CMOS solid state physics, standard cell libraries, and DFT/Scan/MBIST. Required skills include proficiency in scripting languages like Python, Perl, TCL, or Bash. This role focuses on the technical challenge of building hardware to enable global connectivity through the Starlink satellite network.

Skills

ASIC RTL2GDSII Physical Design Static Timing Analysis STA Floorplanning Place and Route DFT Scan MBIST LBIST Python TCL Perl Bash Makefile EDA Tools FinFET CMOS

What you'll do

  • Perform partition synthesis and physical implementation steps including floorplanning, power/ground grid generation, and place and route.
  • Execute signoff checks for timing, noise, physical verification, electromigration, and voltage drop.
  • Develop and improve physical design methodologies and automation scripts for various implementation steps.
  • Conduct architectural feasibility studies to establish timing, power, and area design targets.
  • Resolve complex design, timing, and congestion issues while identifying and driving technical solutions.
  • Debug and fix signoff closure issues in static timing analysis (STA) and logic equivalency.

What we're looking for

  • Bachelor's degree in electrical engineering, computer engineering, or computer science.
  • 1+ years of professional experience working on RTL2GDSII physical design and/or physical design flow development.
  • Ability to work extended hours and weekends as needed to meet critical project milestones.
  • Must be a U.S. citizen, national, lawful permanent resident, refugee, or asylee (or eligible for such status) per ITAR regulations.
  • Experience with industry standard EDA tools including understanding of their capabilities and underlying algorithms (preferred).
  • Knowledge of deep sub-micron FinFET and CMOS solid state physics (preferred).
  • Understanding of CMOS digital design principles, standard cell functionality, and power dissipation in deep submicron processes (preferred).
  • Familiarity with CMOS analog circuit and physical design, DFT/Scan/MBIST/LBIST, and scripting languages like Python or TCL (preferred).

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