Physical Design Engineer, Silicon Engineering

SpaceX

Confirmed live today High trust

Quick summary

Work type
On-site
Location
Irvine, CA
Salary
$125,000–$160,000 / yr
Posted
3 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $197k
This role $142k
$111k most similar roles pay here $259k

This role pays less than 90% of similar roles. Most pay $167,462–$227,500 — the shaded band above. At the midpoint, this role pays about $142k versus about $197k for comparable roles.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 689 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 450 roles with salary data.

Most-posted roles

View all roles at SpaceX

At a glance

TL;DR · Physical Design Engineer, Silicon Engineering

Role Posting Log in to save

The Physical Design Engineer (Silicon Engineering) joins a cross-disciplinary team to develop next-generation ASICs for space and ground infrastructure. This role focuses on building advanced hardware that enables global connectivity through the Starlink network. Day-to-day responsibilities include performing partition synthesis, floorplanning, power/ground grid generation, place and route, and various signoff checks such as static timing analysis, noise, physical verification, electromigration, and voltage drop. The engineer will also develop automation scripts and collaborate on architectural feasibility studies to resolve design and congestion issues. Required skills include experience with RTL2GDSII flows, industry-standard EDA tools, and scripting languages like Python, Perl, Tcl, or Bash. Technical knowledge must include deep sub-micron FinFET and CMOS solid state physics, standard cell libraries, and DFT/Scan/MBIST impacts on physical design flows to ensure high-performance chip implementation for satellite communications.

Skills

ASIC RTL2GDSII Physical Design STA EDA Tools Python TCL Perl Bash Makefile FinFET CMOS DFT Scan MBIST LBIST Floorplanning Place and Route Synthesis

What you'll do

  • Perform partition synthesis and physical implementation steps including floorplanning, power/ground grid generation, and place and route.
  • Execute signoff checks for timing, noise, physical verification, electromigration, voltage drop, and logic equivalency.
  • Develop and improve physical design methodologies and automation scripts for various implementation steps.
  • Conduct architectural feasibility studies with the ASIC design team to establish timing, power, and area targets.
  • Resolve complex design, timing, and congestion issues while identifying and driving technical solutions.
  • Debug and fix signoff closure issues in static timing analysis (STA) and physical verification flows.

What we're looking for

  • Bachelor's degree in electrical engineering, computer engineering, or computer science.
  • 1+ years of professional experience working on RTL2GDSII physical design and/or physical design flow development.
  • Must be a U.S. citizen, national, lawful permanent resident, or eligible for required export control authorizations.
  • Experience with industry standard EDA tools including understanding of their capabilities and underlying algorithms (preferred).
  • Knowledge of deep sub-micron FinFET and CMOS solid state physics (preferred).
  • Understanding of CMOS digital design principles, standard cell functionality, and power dissipation in deep submicron processes (preferred).
  • Familiarity with CMOS analog circuit and physical design (preferred).
  • Basic knowledge of DFT/Scan/MBIST/LBIST and good scripting skills in csh, bash, Perl, Python, TCL, or Makefile (preferred).

Related searches

More Physical Design Engineer jobs Physical Design Engineer jobs in Irvine All jobs at SpaceX

More like this

Similar roles

Physical Design Engineer, Silicon Engineering

SpaceX

Austin, TX 3 days ago
ASIC Physical Design RTL2GDSII Static Timing Analysis STA EDA Tools Python TCL Perl Bash Makefile FinFET CMOS DFT Scan MBIST LBIST Floorplanning Place and Route Physical Verification
1+ yrs exp
Save

Physical Design Engineer, Silicon Engineering

SpaceX

Palo Alto, CA 3 days ago $135,000–$175,000
ASIC RTL2GDSII Physical Design Static Timing Analysis STA Floorplanning Place and Route DFT Scan MBIST LBIST Python TCL Perl Bash Makefile EDA Tools FinFET CMOS
1+ yrs exp
Save

Physical Design Engineer II, Silicon Engineering

SpaceX

Austin, TX 136 days ago
ASIC Physical Design RTL2GDSII Static Timing Analysis STA EDA Tools Python TCL Perl Bash Makefile FinFET CMOS DFT Scan MBIST LBIST Floorplanning Place and Route Synthesis
3+ yrs exp
Save

Physical Design Engineer II, Silicon Engineering

SpaceX

Irvine, CA 153 days ago $145,000–$195,000
ASIC RTL2GDSII Physical Design STA EDA Tools Python TCL Perl Bash Makefile FinFET CMOS DFT Scan MBIST LBIST Floorplanning Place and Route Synthesis
3+ yrs exp
Save

Physical Design Engineer II, Silicon Engineering

SpaceX

Palo Alto, CA 136 days ago $155,000–$210,000
ASIC RTL2GDSII Physical Design STA EDA Tools Python TCL Perl Bash Makefile FinFET CMOS DFT Scan MBIST LBIST Floorplanning Place and Route Synthesis
3+ yrs exp
Save

Senior SOC/ASIC Physical Design Engineer

SpaceX

Irvine, CA 111 days ago $165,000–$260,000
ASIC SOC Physical Design RTL2GDSII Static Timing Analysis (STA) EDA Tools Python TCL Perl Bash Makefile DFT Scan MBIST LBIST FinFET CMOS Floorplanning Place and Route Synthesis
5+ yrs exp
Save