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IC Package Design ASIC RFIC Power Integrity EM Simulation Cadence APD+ SIP HFSS SIWave ADS BGA Co-packaged Optics Tapeout Substrate Design Mixed Signal silicon floor plan +11 more Show less

IC Package Design ASIC RFIC Cadence APD+ SIP SIWave HFSS ADS Power Integrity EM Simulation BGA Co-packaged Optics Tapeout Substrate Design Mixed Signal +10 more Show less

Python C/C++ JavaScript Silicon Validation Computer Architecture Digital Design Circuit Analysis Signal Integrity Timing Analysis Fault Analysis Deep Learning Data Analysis Web Development BIOS Drivers Oscilloscope Logic Analyzer +12 more Show less

Analog/Mixed-Signal Circuit Design Transceiver Micro-architecture CMOS PDK PHY Design CDR Clocking Circuits Pre-tapeout Verification Silicon Validation Firmware Loops Post-silicon Validation +5 more Show less

Silicon Photonics Photonic PDK FDTD MODE Cadence Python DWDM CWDM HPC AI DFx Circuit Layout Optical IO Design Automation Data Analysis Package-level Testing +11 more Show less

RTL Design SystemVerilog Verilog Python Go Java C# TypeScript Perl Ruby Shell TCL LLM RAG Agentic Frameworks Static Analysis Linting Verible Slang Verilator Surelog Synthesis Physical Design Place and Route Timing Closure +20 more Show less

Analog/Mixed-Signal Circuit Design Transceiver Micro-architecture CMOS PDK PHY Design CDR Clocking Circuits Pre-tapeout Verification Silicon Validation Post-silicon Validation Firmware Loops +5 more Show less

Silicon Photonics PIC RFIC Lumerical COMSOL HFSS Spectre ADS SerDes PAM4 NRZ MZM Microring Modulators InGaAs InP CTLE Spectrum Analyzers Vector Signal Analyzers High Speed Oscilloscopes BERT Floor Planning +16 more Show less

Silicon Photonics PIC RFIC Lumerical COMSOL HFSS Spectre ADS SerDes PAM4 NRZ MZM Microring Modulators InGaAs InP CTLE Spectrum Analyzers Vector Signal Analyzers High Speed Oscilloscopes BERT Floor Planning +16 more Show less

FPGA RTL SystemVerilog Verilog VHDL Python Microarchitecture CDC RDC LINT LEC Synthesis Xilinx ChipWhisperer PPA Optimization Post-Silicon Validation Test Automation +12 more Show less

Silicon Photonics Optoelectronics Photonics Semiconductor Devices SOI Platforms Python Matlab JMP Circuit Simulation Optical Measurement Device Characterization Statistical Data Analysis Mux/Demux High Order Mode Mitigation Polarization Management +10 more Show less

Silicon Photonics Optoelectronics Photonics Semiconductor Devices SOI Platforms Python Matlab JMP Circuit Simulation Optical Measurement Device Characterization Mux/Demux Statistical Data Analysis +8 more Show less

Verilog System Verilog ASIC SoC RTL Design Python AXI AHB EDA Tools HDL Simulators HDL Lint Tools Synthesis Timing Closure Formality Check Clock Domain Crossing Power Optimization +11 more Show less

ASIC Design FPGA Verilog SystemVerilog VHDL RTL Design Python C/C++ Bash SoC Integration DSP AXI AHB APB VCS Questa IES Spyglass Xilinx Vivado Altera Quartus II Oscilloscope Spectrum Analyzer +17 more Show less

AI ML RTL Design Physical Design Functional Verification x86 EDA Synopsys Cadence Siemens EDA Data Pipelines PPA SoC Development Hardware Design +9 more Show less

Verilog system verilog ASIC Design Flow SoC Design DFT Static Timing Analysis Synthesis UPF CDC RDC Power Gating Clock Gating ARM Firmware Post-Silicon Bring-up +10 more Show less

Verilog System Verilog RTL Design ASIC SoC Python AXI AHB EDA Tools HDL Simulators HDL Lint Tools Synthesis Timing Closure Formality Check Clock Domain Crossing Power Optimization +11 more Show less

ASIC Design FPGA Design SystemVerilog Verilog VHDL RTL Design Python C/C++ Bash DSP AXI AHB APB VCS Questa IES Spyglass Xilinx Vivado Altera Quartus II Oscilloscope Spectrum Analyzer SoC Integration +17 more Show less

RTL Design Verilog System Verilog ASIC SoC Python AXI AHB Synthesis Timing Closure HDL Simulators HDL Lint Tools Clock Domain Crossing Power Optimization Embedded CPU Subsystems +10 more Show less

Verilog System Verilog RTL Design ASIC SoC Synthesis Timing Closure AXI AHB Python HDL Simulators HDL Lint Tools Clock Domain Crossing Power Optimization Embedded CPU Subsystems Formality Check Silicon Bring-up +12 more Show less