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Digital Design Mixed Signal FPGA Silicon Bring-up Characterization Debug MIPI SoundWire I2S SPMI Audio Amplifier Codec Power Converters Micro-architecture Emulation Verification Validation +12 more Show less

Digital Design Mixed Signal Design FPGA Silicon Bring-up Characterization Debug MIPI SoundWire I2S SPMI Audio Amplifier Codec Power Converters Micro-architecture Emulation Verification +11 more Show less

C C++ SystemVerilog Python Perl Ruby FPGA HAPS Xilinx JTAG Logic Analyzers Oscilloscopes UART AMBA AXI AHB APB SPI I2C I3C USB Assembly Linker Scripts Makefile +19 more Show less

FPGA SoC Chiplet RTL Partial Reconfiguration Bitstream Silicon Architecture Memory Hierarchy High-Speed Interconnects Synthesis Place-and-Route System Integration Debug Observability +8 more Show less

SoC RTL Design Microarchitecture PCIe DDR HBM DFT Synthesis Python Perl Agile Post-Silicon Debug Machine Learning Artificial Intelligence +9 more Show less

PCIe NVLink CXL Ethernet USB SERDES Signal Integrity Firmware Drivers Automated Debug Triage Oscilloscopes BERTs Protocol Analyzers Logic Analyzers ATE AI Agents +11 more Show less

SoC ASIC HBM SerDes High-speed I/O Power and Thermal Packaging Post-silicon Bring-up Silicon Validation System Integration Co-design AI Tools +7 more Show less

RTL Verilog SystemVerilog ASIC Design Synthesis Timing Closure CDC RDC UPF AMBA AXI AHB APB Cryptography Low-Power Design Lint Netlist Hardware Security +13 more Show less

UVM System Verilog C-DPI FPGA ASIC Firmware SoC AXI AHB DMA Cryptography Data Compression Silicon Bring-up Emulation Micro-architecture +10 more Show less

Silicon Photonics Waveguide Modeling Optical Coupling Modulators Photodetectors Co-packaged Optics (CPO) Pluggable Optics 800G 1.6T Data Analysis Simulation Characterization Optical Transceivers Photonics Design +9 more Show less

RTL Verilog SystemVerilog ASIC Design CDC RDC UPF Synthesis Timing Closure AMBA AXI AHB APB Cryptography Low-Power Design Lint Netlist +12 more Show less

RTL Verilog SystemVerilog ASIC Design CDC RDC UPF Synthesis Timing Closure AMBA AXI AHB APB Cryptography Low-power Design Lint Netlist Hardware Security +13 more Show less

ASIC SoC RTL-to-GDS Synthesis Floorplanning Clock Tree Synthesis Static Timing Analysis PrimeTime Design Compiler Innovus Fusion Compiler DRC LVS IR Drop Electromigration Python Tcl Shell Scripting FPGA FinFET +15 more Show less

Silicon Photonics PIC RFIC Lumerical COMSOL HFSS Spectre ADS SerDes PAM4 NRZ CPO mixed signal DSP CTLE +10 more Show less

Silicon Photonics PIC Lumerical COMSOL HFSS Spectre ADS RFIC SerDes PAM4 NRZ DSP mixed signal CPO CTLE Spectrum Analyzers +11 more Show less

ASIC SystemVerilog UVM Python MATLAB RTL Pre-silicon Verification Post-silicon Validation Constrained Random Verification DSP Object-Oriented Programming test bench development Functional Coverage Chip Bring-up +9 more Show less

ASIC SystemVerilog UVM Python MATLAB RTL Pre-silicon Verification Post-silicon Validation Chip Bring-up Constrained Random Verification DSP Object-Oriented Programming test bench development Functional Coverage Scripting +10 more Show less

ASIC SystemVerilog UVM Python MATLAB RTL Pre-silicon Verification Post-silicon Validation Constrained Random Verification DSP Object-Oriented Programming test bench development Functional Coverage Chip Bring-up +9 more Show less

ASIC Design Verification UVM OVM VMM RTL Python Constrained Random Verification Test Bench Development Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Digital Design +8 more Show less

ASIC Design Verification UVM OVM VMM RTL Python Constrained Random Verification Test Bench Development Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Digital Design +8 more Show less