Staff Silicon Design Engineer

Amd

Confirmed live today High trust

Quick summary

Work type
On-site
Location
Boxborough, MA
Salary
$178,400–$267,600 / yr
Posted
3 days ago
Freshness
Confirmed live today
Closes
Oct 1, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $204k
This role $223k
$147k most similar roles pay here $281k

This role pays more than 68% of similar roles. Most pay $174,375–$233,050 — the shaded band above. At the midpoint, this role pays about $223k versus about $204k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 512 open roles on FindRole.

Listed pay typically runs $166,400–$249,600 across 512 roles with salary data.

Most-posted roles

View all roles at Amd

At a glance

TL;DR · Staff Silicon Design Engineer

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As a Staff Silicon Design Engineer on the pre-silicon IP design team, you will serve as an IP Design lead to guide a team of engineers through complex technical challenges and ensure successful program delivery. You will be responsible for planning deliverables, designing IP subsystems with integrated third-party components like ARM, DSPs, and NOCs, and performing quality checks including lint, CDC, and power rule checks on power-gated digital designs. The role requires collaborating with SoC teams to support connectivity, DFT, synthesis, constraints, static timing analysis, and post-silicon bring-up. You will utilize Verilog and SystemVerilog for high-speed, multi-clock digital designs while implementing power-saving techniques like clock gating and UPF-based power gating. This role focuses on developing tailored System-on-a-Chip solutions by integrating various building blocks into customized hardware architectures.

Skills

Verilog system verilog ASIC Design Flow SoC DFT Synthesis Static Timing Analysis UPF CDC RDC Power Gating Clock Gating Firmware

What you'll do

  • Guide a team of design engineers through technical challenges and ensure they meet program commitments.
  • Provide technical guidance to the design team on complex engineering issues.
  • Plan and manage team deliverables throughout the entire project lifecycle.
  • Design IP subsystems by integrating AMD and third-party components like ARM, DSPs, and NOCs.
  • Perform quality checks including lint, CDC, and power rule checks for power-gated digital designs.
  • Support design verification, synthesis, constraints, and static timing analysis to ensure successful delivery to SoC.
  • Partner with SoC teams to manage connectivity, DFT, physical design, firmware, and post-silicon bring-up.

What we're looking for

  • Bachelor's or Master's degree in computer engineering or Electrical Engineering.
  • Significant full-time experience in IP hardware design (preferred).
  • Experience in subsystem development with embedded processors and data fabric architectures (preferred).
  • Prior technical leadership as a subject matter expert (preferred).
  • Prior team leadership experience for small or mid-sized teams (preferred).
  • Proficiency in Verilog/SystemVerilog RTL logic design of high-speed, multi-clock digital designs (preferred).
  • Experience with 3rd party IP integration and power saving techniques like clock gating and UPF-based power gating (preferred).
  • Detailed understanding of ASIC design flows, including CDC/RDC concepts and lint tools (preferred).

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