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UVM Formal Verification Python PCIe CXL AMBA CHI Fabric Interconnects Assertions Coverage Simulation Data Analysis Automation AI-driven solutions +9 more Show less

SystemVerilog UVM Verilog C++ C SystemC TLM RTL ASIC Verification Linux Windows Perl Ruby Shell Scripting Makefiles HLS Simulation Graphics Pipeline Architecture +13 more Show less

Power Electronics Hardware Validation DFT SI/PI FPGA Firmware Test Automation I2C SPI CAN DO-160 MIL-STD-810 Requirements Management Radiation Testing +9 more Show less

SystemVerilog UVM VCS Verdi DVE Python Tcl Perl Shell PCIe Ethernet DDR AXI DMA FPGA HAPS UPF C/C++ Make Formal Verification +15 more Show less

Verilog SystemVerilog UVM DFT RTL Design Python Tcl Perl Shell Static Timing Analysis ASIC SoC FPGA Synopsys Cadence PCIe SerDes HBM Synthesis Place-and-Route +15 more Show less

UVM SystemC DPI-C C Matlab Formal Verification Scripting Modem Design pre silicon post silicon AI/LLM CMOS +7 more Show less

ASIC Design Verification UVM OVM VMM Python RTL Design Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Coverage Models Scripting Digital Design +10 more Show less

ASIC Design Verification UVM OVM VMM Python RTL Design Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Functional Coverage Test Plans Scripting +10 more Show less

ASIC Design Verification UVM OVM VMM Python RTL Design Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Functional Coverage +8 more Show less

ASIC Design Verification UVM OVM VMM Python RTL Design Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Test Bench Development Functional Coverage Test Plans Scripting +10 more Show less

C++ SystemVerilog UVM Python Verilog RTL Design Verification Scripting Perl AI-driven development Testbench Infrastructure Coverage Closure +7 more Show less

UVM C/C++ Formal Verification System C DPI-C Matlab RTL FPGA Emulation Scripting DSP CMOS +7 more Show less

SystemVerilog UVM VCS Verdi DVE Python Tcl Perl Shell PCIe Ethernet DDR AXI DMA FPGA HAPS UPF C/C++ Make Formal Verification +15 more Show less