Browse tech roles

Basic role filtering by workplace, salary floor, and post age. For full AI matching and advanced filtering upload your resume using AI Match.

Active Keyword: SR Design Verification Engineer Remove filter Clear all

7 of up to 20 (filtered)

Senior Staff Design Verification Engineer

Amd

San Jose, CA 8 days ago $200,000–$300,000
Actively hiring Confirmed live 2 days ago High trust Above market
DFT Verilog SystemVerilog ATPG Scan MBIST LBIST Boundary Scan UVM OVM RTL Design Static Timing Analysis Python Tcl Perl Shell Synopsys DFT Compiler TestMAX PrimeTime VCS Cadence tool s FPGA
Hybrid
Save

Senior ASIC Design Verification Engineer

SpaceX

Austin, TX 60 days ago
Actively hiring Confirmed live 2 days ago Low trust
ASIC Design Verification UVM OVM VMM RTL Python Constrained Random Verification Test Bench Development Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Digital Design
5+ yrs exp
Save

Senior ASIC Design Verification Engineer

SpaceX

Redmond, WA 60 days ago $165,000–$260,000
Actively hiring Confirmed live 2 days ago Low trust Above market
ASIC Design Verification UVM OVM VMM RTL Python Constrained Random Verification Test Bench Development Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Digital Design
5+ yrs exp
Save

Senior ASIC Design Verification Engineer

SpaceX

Palo Alto, CA 60 days ago $175,000–$280,000
Actively hiring Confirmed live yesterday Low trust Above market
ASIC UVM OVM VMM RTL Python Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Test Bench Development Object-Oriented Programming Digital Design
5+ yrs exp
Save

Senior ASIC Design Verification Engineer

SpaceX

Irvine, CA 60 days ago $165,000–$260,000
Actively hiring Confirmed live yesterday Low trust Above market
ASIC Design Verification UVM OVM VMM RTL Python Constrained Random Verification test bench development Pre-silicon Verification Post-silicon Validation Chip Bring-up Object-Oriented Programming Scripting Functional Coverage
5+ yrs exp
Save

Senior ASIC Design Verification Engineer

Amazon Inc

Sunnyvale, CA +1 78 days ago $159,200–$215,300
Actively hiring Confirmed live 2 days ago High trust Above market
UVM C++ C System C DPI-C Formal Verification Matlab RTL FPGA Emulation Digital Verification ASIC Scripting CMOS
7+ yrs exp
Save

Senior Design Verification Engineer

Amd

Santa Clara, CA 95 days ago $141,760–$212,640
Actively hiring Confirmed live 2 days ago High trust Competitive pay
SystemVerilog UVM VCS Verdi DVE Python Tcl Make PCIe Ethernet DDR AXI DMA Shell Perl C/C++ Formal Verification UPF FPGA HAPS
Hybrid
Save