Senior Design Verification Engineer

Amd

Confirmed live today Trusted

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $141,760–$212,640 / yr
Posted: 140 days ago
Freshness: Confirmed live today
Closes: Jun 8, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $204k

This role $177k

$130k $250k

below market most similar roles pay here above market

This role pays less than 73% of similar roles. Most pay $169,625–$238,700 — the blue band above. At the midpoint, this role pays about $177k versus about $204k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 496 open roles on FindRole.

Listed pay typically runs $172,000–$258,000 across 496 roles with salary data.

Most-posted roles

View all roles at Amd

At a glance

TL;DR · Senior Design Verification Engineer

Role Posting Log in to save

The SR Design Verification Engineer joins the Network Technologies Solutions Group to drive verification closure on complex, high-performance ASIC designs for next-generation networking products. This role involves developing robust UVM-based testbench architectures for IP, subsystem, and SoC-level verification. Key responsibilities include creating test plans, developing SystemVerilog components like stimulus generators and scoreboards, and performing regression triage to root-cause architectural, functional, and performance issues. The candidate will utilize industry-standard tools including VCS, Verdi, and DVE, while employing scripting languages such as Python, Tcl, and Perl for automation. Technical expertise must cover protocols like PCIe, DDR, Ethernet, and AXI. The work focuses on solving data-path and networking challenges within a distributed services platform, requiring deep knowledge of constrained-random methodologies and high-speed I/O pipelines.

What does a Design Verification Engineer earn in California?

Median $199500 from 57 postings across 7 companies.

See salary data

Skills

SystemVerilog UVM VCS Verdi DVE Python Tcl Perl Shell PCIe Ethernet DDR AXI DMA FPGA HAPS UPF C/C++ Make Formal Verification

What you'll do

Develop robust UVM-based testbench architectures for IP, subsystem, and SoC-level verification.
Create test plans, feature mappings, and coverage strategies for complex networking and data-path IP.
Develop SystemVerilog components including stimulus generators, agents, scoreboards, checkers, and assertions.
Execute verification plans, triage regressions, and debug architectural, functional, and performance issues.
Root-cause complex failures across RTL, testbench, and interfaces like PCIe, DDR, and Ethernet.
Optimize simulation performance, coverage closure, and verification sign-off methodologies.
Improve verification infrastructure and automation using Python, Tcl, or Shell scripting.
Provide technical leadership and mentorship to junior verification engineers.

What we're looking for

Bachelor’s Degree in Electrical/Computer Engineering or related field.
Master’s Degree (preferred).
Expert-level knowledge of SystemVerilog and UVM.
Strong hands-on experience with SystemVerilog simulators (VCS preferred) and waveform debuggers (Verdi/DVE).
Proven experience verifying complex IP/subsystems using test plans, coverage, and constrained-random methodologies.
Experience with industry protocols such as PCIe, AXI, Ethernet, DDR, DMA engines, or similar data-path components.
Scripting skills in Python, Perl, Shell, Tcl, or equivalent for automation and infrastructure.
Experience with performance verification, power-aware verification (UPF), or formal verification (preferred).

Similar roles

Senior Design Verification Engineer

Amd

Santa Clara, CA +1 45 days ago $141,760–$212,640

SystemVerilog UVM VCS Verdi DVE Python Tcl Perl Shell PCIe Ethernet DDR AXI DMA FPGA HAPS UPF C/C++ Make Formal Verification

Hybrid

Save

SoC Design Verification Engineer

Amd

San Jose, CA 90 days ago $141,760–$212,640

System Verilog Verilog UVM C++ C Python Perl SOC Architecture Computer Architecture AXI AHB PCIe DDR Functional Verification Performance Verification Code Coverage Functional Coverage

Save

SOC Design Verification Engineer

Qualcomm

San Diego, CA 21 days ago $121,800–$182,600

System Verilog UVM C Assertion-Based Verification (SVA) Coverage-Driven Verification Python Formal Verification Portable Stimulus (PSS) PCIe CXL DDR HBM Ethernet Veloce Palladium ZeBu RTL SoC Architecture AI/ML Accelerators

2+ yrs exp

Save

Senior Silicon Design Verification Engineer

Amd

Austin, TX 33 days ago $144,800–$217,200

SystemVerilog UVM Verilog C++ C SystemC TLM RTL ASIC Verification Linux Windows Perl Ruby Shell Scripting Makefiles HLS Simulation Graphics Pipeline Architecture

Save

Design Verification Engineer

Apple Inc

Austin, TX 136 days ago

UVM System Verilog Python C++ System C Perl Coverage Driven Verification SVA Constraint Random Testing LLM ML RTL Simulation AXI AHB NoC 3GPP 4G 5G

10+ yrs exp

Save

Design Verification Engineer

Apple Inc

Austin, TX 136 days ago

UVM System Verilog Python C++ System C Perl Coverage Driven Verification SVA LLM ML 4G 5G 3GPP AXI AHB NOC Bus Fabric RTL Simulation

Save