Senior Design Verification Engineer

Amd

Confirmed live 2 days ago High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Santa Clara, CA
Salary
$141,760–$212,640 / yr
Posted
95 days ago
Freshness
Confirmed live 2 days ago
Closes
Jun 8, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $187k
This role $177k
$130k most similar roles pay here $230k

This role pays less than 64% of similar roles. Most pay $159,750–$214,175 — the shaded band above. At the midpoint, this role pays about $177k versus about $187k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 367 open roles on FindRole.

Listed pay typically runs $166,400–$249,600 across 367 roles with salary data.

Most-posted roles

View all roles at Amd

At a glance

TL;DR · Senior Design Verification Engineer

Role Posting Log in to save

SR Design Verification Engineer The SR Design Verification Engineer joins the Network Technologies Solutions Group to drive verification closure on complex, high-performance ASIC designs within a distributed services platform. This role involves developing robust UVM-based testbench architectures for IP, subsystem, and SoC levels while creating test plans and coverage strategies for networking and data-path components. The engineer will build SystemVerilog components including stimulus generators, scoreboards, and assertions, while performing regression triage and root-cause analysis for RTL and interface issues like PCIe, DDR, and Ethernet. Technical requirements include expert knowledge of SystemVerilog and UVM, proficiency with VCS and Verdi tools, and scripting skills in Python, Tcl, or Shell. The role addresses technical challenges in high-performance networking products, specifically focusing on data-path components, high-speed I/O pipelines, and performance verification for advanced data center networking technology.

Skills

SystemVerilog UVM VCS Verdi DVE Python Tcl Make PCIe Ethernet DDR AXI DMA Shell Perl C/C++ Formal Verification UPF FPGA HAPS

What you'll do

  • Develop robust UVM-based testbench architectures for IP, subsystem, and SoC-level verification.
  • Create comprehensive test plans, feature mapping, and coverage strategies for networking and data-path IPs.
  • Build high-quality SystemVerilog components including stimulus generators, scoreboards, checkers, and assertions.
  • Execute verification plans, triage regressions, and debug architectural, functional, and performance issues.
  • Root-cause complex failures across RTL, testbench, and interfaces like PCIe, DDR, and Ethernet.
  • Optimize simulation performance, coverage closure, and verification sign-off methodologies.
  • Develop automation scripts and infrastructure enhancements using Python, Tcl, or Shell.
  • Provide technical leadership and mentorship to junior engineers within the verification team.

What we're looking for

  • Bachelor's Degree in Electrical/Computer Engineering or a related field.
  • Master's degree is preferred.
  • Expert-level knowledge of SystemVerilog and UVM.
  • Experience with SystemVerilog simulators (VCS preferred) and waveform debuggers (Verdi/DVE).
  • Proven experience verifying complex IP/subsystems using test plans, coverage, and constrained-random methodologies.
  • Experience with industry protocols such as PCIe, AXI, Ethernet, DDR, or DMA engines.
  • Scripting skills in Python, Perl, Shell, Tcl, or equivalent for automation and infrastructure.
  • Preferred experience in performance verification, power-aware verification (UPF), formal verification, or FPGA/HAPS-based flows.

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