Senior Design Verification Engineer

Amd

Confirmed live yesterday High trust

Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CA
Salary: $200,000–$300,000 / yr
Posted: 91 days ago
Freshness: Confirmed live yesterday
Closes: Jul 2, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $201k

This role $250k

$132k most similar roles pay here $318k

This role pays more than 88% of similar roles. Most pay $173,867–$227,900 — the shaded band above. At the midpoint, this role pays about $250k versus about $201k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 374 open roles on FindRole.

Listed pay typically runs $166,400–$249,600 across 374 roles with salary data.

Most-posted roles

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At a glance

TL;DR · Senior Design Verification Engineer

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Sr. Design Verification Engineer joins the CPU testbench infrastructure team to build scalable verification environments for next-generation server processors. This role involves developing and enhancing CPU-level testbenches used by core verification and debug teams to validate complex subsystems while collaborating with globally distributed engineering teams. The engineer will develop, maintain, and enhance tests and components using C++, SystemVerilog, and UVM. Key responsibilities include debugging testbench and design issues using software models, contributing to coverage closure, and integrating infrastructure into broader workflows. The role utilizes modern methodologies including AI-driven development and debug techniques. Required skills include C/C++ programming, RTL design knowledge in Verilog, and scripting in Python or Perl. The position focuses on the technical challenge of providing robust infrastructure for CPU microarchitecture validation within the server processor domain.

What does a Design Verification Engineer earn?

Median $195800 from 64 postings across 10 companies.

See salary data

Skills

C++ SystemVerilog UVM Python Perl RTL Verilog Design Verification Scripting AI-driven development Coverage Closure

What you'll do

Develop and maintain CPU-level testbench infrastructure using C++.
Build scalable verification environments to support CPU subsystems and core-level validation.
Write and enhance tests and components using SystemVerilog and UVM.
Debug testbench and design issues using software models and analysis tools.
Contribute to verification quality metrics and coverage closure.
Integrate testbench infrastructure with broader verification workflows.
Apply AI-driven techniques to improve verification efficiency and accelerate product delivery.

What we're looking for

Develop and maintain CPU-level testbench infrastructure using C++.
Build scalable verification environments supporting CPU subsystems and core-level validation.
Write and enhance tests and components using C++, SystemVerilog, and UVM.
Debug testbench and design issues using software models and analysis tools.
Contribute to verification quality metrics and coverage closure.
Strong C/C++ programming and software development skills (preferred).
Experience building or maintaining verification testbenches (preferred).
Masters degree in Electrical Engineering.

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