Senior Design Verification Engineer

Amd

Confirmed live yesterday High trust

Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CAAustin, TX
Salary: $141,760–$212,640 / yr
Posted: 4 days ago
Freshness: Confirmed live yesterday
Closes: Sep 11, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $192k

This role $177k

$132k most similar roles pay here $235k

This role pays less than 68% of similar roles. Most pay $168,500–$216,250 — the shaded band above. At the midpoint, this role pays about $177k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 379 open roles on FindRole.

Listed pay typically runs $166,400–$249,600 across 379 roles with salary data.

Most-posted roles

View all roles at Amd

At a glance

TL;DR · Senior Design Verification Engineer

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Sr. Design Verification Engineer The Sr. Design Verification Engineer joins the Network Technologies Solutions Group to drive verification closure on complex, high-performance ASIC designs for data center networking products. This role involves developing robust UVM-based testbench architectures, creating test plans, and building SystemVerilog components such as stimulus generators, scoreboards, and assertions for IP, subsystem, and SoC levels. The engineer will perform regression triage, root-cause architectural and RTL issues, and optimize simulation coverage. Key technical requirements include expert knowledge of SystemVerilog and UVM, proficiency with VCS and Verdi tools, and experience with protocols like PCIe, DDR, and Ethernet. Additionally, the role requires scripting skills in Python, Tcl, or Shell to enhance infrastructure. The work focuses on high-performance data-path components and networking pipelines within a distributed services platform for cloud and enterprise environments.

What does a Design Verification Engineer earn?

Median $177300 from 31 postings across 8 companies.

See salary data

Skills

SystemVerilog UVM VCS Verdi DVE Python Tcl Make Perl Shell PCIe Ethernet DDR AXI DMA UPF Formal Verification FPGA HAPS C/C++

What you'll do

Develop robust UVM-based testbench architectures for IP, subsystem, and SoC-level verification.
Create comprehensive test plans, feature mapping, and coverage strategies for complex networking data-path IPs.
Build high-quality SystemVerilog components including stimulus generators, scoreboards, checkers, and functional coverage models.
Execute verification plans while performing regression triage and debugging architectural, functional, and performance issues.
Root-cause complex failures across RTL, testbench, and interfaces such as PCIe, DDR, and Ethernet.
Optimize simulation performance, coverage closure, and overall verification sign-off methodologies.
Develop automation scripts using Python, Tcl, or Shell to enhance verification infrastructure.
Provide technical leadership and mentorship to junior engineers within the verification team.

What we're looking for

Bachelor's Degree in Electrical/Computer Engineering or related field; Master's degree (preferred).
Expert-level knowledge of SystemVerilog and UVM.
Experience with SystemVerilog simulators (VCS preferred) and waveform debuggers (Verdi/DVE).
Proven experience verifying complex IP/subsystems using test plans, coverage, and constrained-random methodologies.
Strong debugging skills across architecture, RTL, and testbench layers.
Experience with industry protocols such as PCIe, AXI, Ethernet, DDR, or DMA engines.
Scripting skills in Python, Perl, Shell, Tcl, or equivalent for automation and infrastructure.
Experience with performance verification, power-aware verification (UPF), formal verification, or FPGA/HAPS flows (preferred).