Browse tech roles

Basic role filtering by workplace, salary floor, and post age. For full AI matching and advanced filtering upload your resume using AI Match.

Active Keyword: Process Design Remove filter Clear all

6 of up to 20 (filtered)

Graphics & AI Processor Design Engineer

Amd

Austin, TX 9 days ago $178,400–$267,600
Actively hiring Confirmed live yesterday High trust Above market
GPU ASIC Design EDA Tools VCS Cadence Mentor Graphics LINT CDC Tape-out Digital Design
Hybrid
Save

Processor Design Verification Engineer

Qualcomm

San Diego, CA 87 days ago $127,200–$190,800
Actively hiring Confirmed live yesterday High trust Below market
SystemVerilog Digital Design Verification Object-Oriented Programming DSP NPU Cache Memory Coherency Bus Protocol Processor Integration SoC
2+ yrs exp
Save

Processor Micro Architect RTL Design Engineer

Qualcomm

San Diego, CA 87 days ago $180,400–$270,600
Actively hiring Confirmed live 2 days ago Trusted Above market
RTL Verilog System Verilog ASIC Design Logic Design Digital Design Static Timing Analysis Low Power Design Microprocessor Architecture Cache Bus Protocol Linting Clock Domain Crossing GDS2 Synthesis Simulation Regression
6+ yrs exp
Save

Senior FPGA / RTL Design Engineer, Signal Processing

Motorola Solutions

Los Angeles, CA +1 95 days ago $125,000–$195,000
Actively hiring Confirmed live yesterday Trusted Below market
FPGA Digital Signal Processing RTL Xilinx Vivado MATLAB Logic Analyzers Hardware Verification Timing Closure Synthesis Simulation Test Bench Development MIMO
6+ yrs exp Hybrid
Save

Principal FPGA / RTL Design Engineer, Signal Processing

Motorola Solutions

Los Angeles, CA +1 102 days ago $175,000–$225,000
Actively hiring Confirmed live 2 days ago High trust Competitive pay
FPGA RTL Design Xilinx Vivado Digital Signal Processing Python Perl MATLAB Logic Analyzers Timing Closure Simulation test bench development Wireless Communication Systems
10+ yrs exp Hybrid
Save

Processor ASIC RTL Design Engineer

Qualcomm

San Diego, CA 126 days ago $127,200–$190,800
Actively hiring Confirmed live 2 days ago Trusted Below market
RTL system Verilog Verilog ASIC Design Logic Design Digital Design Static Timing Analysis Clock Domain Crossing Microprocessor Design Bus Interface Cache Linting LEC CLP GDS2 Synthesis
2+ yrs exp
Save