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Principal FPGA / RTL Design Engineer - Signal Processing

Motorola Solutions

Los Angeles, CA 3 days ago $175,000–$225,000
Actively hiring Posted this week Verified listing Competitive pay
Vivado Xilinx FPGA RTL Python Perl MATLAB Fixed_point_design Multiple_clock_domain_FPGA_designs Digital_signal_processing Wireless_communication_systems
Hybrid
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Processor ASIC RTL Design Engineer

Qualcomm

San Diego, CA 27 days ago $127,200–$190,800
Actively hiring Below market
SystemVerilog RTL Verilog Linting CDC LEC CLP Processor integration Bus interface Cache Digital design Logic design
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Processor Micro Architect RTL Design Engineer (Multiple Levels)

Qualcomm

San Diego, CA 27 days ago $180,400–$270,600
Actively hiring Above market
Verilog System Verilog RTL digital design logic design cache memory coherency bus interface multi-core microprocessor architecture low power design functional verification static timing analysis formal verification PLDRC clock domain crossing
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