Circuit Design Engineer, Library/Process Monitor

Apple Inc

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Work type: On-site
Location: Beaverton, OR
Posted: 83 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

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TL;DR · Circuit Design Engineer, Library/Process Monitor

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As a Circuit Design Engineer - Library/Process Monitor within the Digital Design Engineering group, you will join the custom digital circuits team to support processor design efforts using deep submicron technologies. You will be responsible for driving transistor level circuit design, modeling, and performance analysis to improve overall Library PPA. Your daily work involves developing standard cell circuits, performing layout optimization to reduce parasitics, and designing process monitor IP on PNR blocks. You will collaborate with CPU, SOC, and GPU teams to meet physical design requirements across various technology, architecture, and PDK releases. Key technical skills include experience with high-performance flip flops, level shifters, retention flops, RTL2GDSII flow, and Static Timing Analysis to ensure functional products reach customers quickly.

Skills

Circuit Design Standard Cell Library PPA Layout Optimization PNR RTL2GDSII Static Timing Analysis STA Process Monitor IP PDK SOC GPU CPU Flip Flops Level Shifters

What you'll do

Drive library architecture discussions and optimization efforts to improve overall Library PPA.
Identify and reduce parasitics to push circuit PPA through layout optimization.
Manage Library PPA for various technologies, architectures, and PDK releases.
Develop standard cell circuits that push design PPA boundaries.
Design process monitor IP on PNR blocks and validate other IPs in testchips.
Communicate physical design requirements to CPU, SOC, and GPU teams.

What we're looking for

Minimum of 3 years of experience.
Experience in circuit design of high-performance flip flops, level shifters, retention flops, and other complex circuits (preferred).
Experience in RTL2GDSII flow and/or Static Timing Analysis (STA) (preferred).
Bachelor's Degree.

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