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CPU Architecture RTL Physical Design VLSI Circuit Design Power Management High-Frequency Design Advanced Packaging SoC Design Power Delivery Process Technology +6 more Show less

Physical Design ASIC SoC Cadence Innovus Synopsys Fusion Compiler Synopsys PrimeTime SI Python TCL Perl C/C++ Shell Scripting Linux Unix Clock Tree Synthesis Static Timing Analysis RC Extraction DFT Signal Integrity Floorplanning Routing +15 more Show less

Arm AI Robotics Autonomous Vehicles ROS 2 Embedded Linux Heterogeneous Compute Simulation Sensor Fusion Inference Serving Functional Safety Linux Profiling Observability +9 more Show less

Data Architecture Physical AI Machine Learning Edge Computing CI/CD Agile SDLC Streaming Data Digital Twin Sensor Data Telemetry Test Automation +6 more Show less

ASIC SoC Physical Design RTL-to-GDSII Synthesis Place & Route STA Timing Closure Power Optimization TCL Python Synopsys Cadence PPA EM/IR Advanced Nodes +10 more Show less

Physical Design Floorplanning Place and Route Power Grid EMIR Formal Verification DRC LVS DFM STA Conformal LP LEC RedHawk Calibre Perl TCL CMOS Computer Architecture +13 more Show less

Physical Design Floorplanning Place and Route Power Grid EM/IR Formal Verification DRC LVS DFM STA Conformal LP LEC RedHawk Calibre Perl TCL CMOS Computer Architecture +13 more Show less

Physical Design Place and Route Floorplanning Power Grid EM/IR Formal Verification DRC LVS STA Conformal LP LEC RedHawk Calibre Perl TCL CMOS Layout Design DFM +13 more Show less

ASIC Physical Design Floorplanning Power Planning Clock Tree Synthesis Static Timing Analysis Signal Integrity RC Extraction DFT UPF Python Tcl Perl Shell Linux Unix Cadence Innovus Synopsys Fusion Compiler Synopsys PrimeTime +14 more Show less

Python Data Analysis Data Visualization Dashboards

Python Claude Innovus ICC2 Calibre Tcl Docker OpenAI API Pinecone Weaviate RAG LLM MLPD STA DRC EDA Tools Vector Databases +12 more Show less

VLSI Physical Design Floorplanning Place and Route Static Timing Analysis Clock Tree Synthesis Power Integrity IR Drop Analysis Physical Verification DRC LVS RC Extraction Synthesis ICC2 PrimeTime dc_shell Innovus Synopsys Cadence Mentor Perl C C++ TCL Linux Python SKILL Make +23 more Show less

Physical Design Place and Route Floorplanning Power Grid EM/IR Formal Verification DRC LVS STA Conformal LP LEC RedHawk Calibre Perl TCL CMOS Layout Design DFM +13 more Show less

DRC LVS PERC ESD Calibre ICV Pegasus ASIC Physical Design Python TCL Perl Bash Makefile SoC DFT tapeout Advanced Nodes Rule Deck Validation +14 more Show less

DRC LVS ESD PERC Calibre ICV Pegasus ASIC SoC Python TCL Perl Bash Makefile Physical Design tapeout DFT SerDes DDR Advanced Nodes +15 more Show less

DRC LVS ESD PERC Calibre ICV Pegasus ASIC Physical Design Python TCL Perl Bash Makefile SoC DFT RDL tapeout Advanced Nodes AI Agents +15 more Show less