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Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software
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As a CPU Full-chip Physical Integration Engineer within the Silicon Engineering Group, you will participate in the physical design, integration, and verification of high performance, low power processor development. Your daily responsibilities include managing full chip floorplans, area optimizations, block partitioning, pin placements, and place and route processes. You will construct and verify final CPU layout databases, develop and validate Power Grids with routability analysis, and drive custom layout integration alongside EM/IR and formal verification. To achieve signoff closure for tapeout, you will collaborate with implementation, CAD, and SOC teams while developing physical design methodologies. Required skills include proficiency in Perl or TCL scripting and knowledge of CMOS circuit design. You will utilize tools such as Conformal LP, LEC, HardRock, and Calibre to solve complex integration challenges within the processor domain.
Perform full chip floorplanning, area optimizations, block partitioning, and pin placements.
Manage chip level place and route (PnR) and final layout database construction and verification.
Develop and validate the power grid including routability analysis.
Drive custom layout integration and perform EM/IR electrical verification and formal verification.
Coordinate with implementation and CAD teams to achieve signoff closure for tapeout.
Collaborate with the SOC team to meet specific IP technical and delivery requirements.
Establish CAD and physical design methodologies and flow development for chip integration.
Create scripts to automate tasks and improve debug efficiency.
What we're looking for
Minimum BS degree and 10+ years of relevant industry experience.
Experience with scripting in Perl or TCL.
Knowledge of industrial standards in Physical Design, including Floorplanning, Partitioning, Budgeting, Place and Route, and Physical Verification (preferred).
Experience in developing and implementing Power Grid and Clock specifications (preferred).
Solid knowledge of Low Power Design, Physical Construction, Integration, EMIR, SIGEM Analysis, Formal Verification, Physical PDV, DRC/LVS Verification, and DFM (preferred).
Solid understanding of verification tools such as Conformal LP, LEC, RedHawk, and Calibre (preferred).
Solid understanding of CMOS circuit design with a layout design background (preferred).
Working knowledge of Extraction and STA methodology, tools, and Computer Architecture (preferred).
Physical Design
RTL-to-GDS
Logic Synthesis
place-and-route
STA
Power Analysis
Perl
TCL
floor-planning
Digital Circuits
Memory Macros
Standard Cells
Deep Sub-micron Technology