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Active Keyword: Integration Design Remove filter Clear all

15 of up to 20 (filtered)

GPU Design Integration Engineer

Qualcomm

San Diego, CA 10 days ago $195,200–$292,800
Actively hiring Confirmed live yesterday High trust Above market
ASIC RTL Design SystemVerilog Synthesis Logic Design Micro-architecture AMBA AXI AHB APB Python Low Power Design CDC Lint
6+ yrs exp
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Hardware Systems Design & Integration Engineer

Apple Inc

Cupertino, CA 20 days ago $150,400–$277,600
Actively hiring Confirmed live yesterday High trust Above market
Layout Digital Design Signal Integrity Power Integrity RF SoC Integration Embedded Systems Oscilloscopes Spectrum Analyzers Frequency Counters Manufacturing Test
5+ yrs exp
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RTL Design & Integration Engineer

Amd

San Jose, CA 20 days ago $166,400–$249,600
Actively hiring Confirmed live 2 days ago High trust Above market
Verilog SystemVerilog RTL Design VLSI FPGA Python Tcl Perl Shell Synopsys Design Compiler Primetime VCS Cadence Virtuoso UVM OVM STA Synthesis P&R GDSII Simulation
Hybrid
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ASIC Design and Integration Engineer, Silicon Security

Apple Inc

Cupertino, CA 22 days ago $184,700–$324,800
Actively hiring Confirmed live yesterday Trusted Above market
RTL Verilog SystemVerilog ASIC Design Synthesis Timing Closure CDC RDC UPF AMBA AXI AHB APB Cryptography Low-Power Design Lint Netlist Hardware Security
10+ yrs exp
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ASIC Design Engineer, IP Integration & Implementation

Apple Inc

Sunnyvale, CA 22 days ago $150,400–$277,600
Actively hiring Confirmed live yesterday Trusted Above market
RTL ASIC Design AMBA AXI AHB APB UPF Python Perl TCL Logic Synthesis Static Timing Analysis Formal Verification Floorplanning Timing Closure Low-Power Design
3+ yrs exp
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ASIC Design and Integration Engineer

Apple Inc

Cupertino, CA 32 days ago $129,300–$194,700
Actively hiring Confirmed live yesterday Low trust Below market
SystemVerilog RTL Design ASIC Design Synthesis Timing Analysis Power Optimization Formal Verification CDC RDC PPA Micro-architecture Digital Design
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ASIC Design and Integration Engineer

Apple Inc

Beaverton, OR 32 days ago
Actively hiring Confirmed live 2 days ago Trusted
SystemVerilog RTL Design ASIC Design Synthesis Timing Analysis Power Optimization CDC RDC Formal Verification Simulation Micro-architecture
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ASIC Design and Integration Engineer, Silicon Security

Apple Inc

Cupertino, CA 38 days ago $150,400–$277,600
Actively hiring Confirmed live yesterday Trusted Above market
RTL Verilog SystemVerilog ASIC Design CDC RDC UPF Synthesis Timing Closure AMBA AXI AHB APB Cryptography Low-Power Design Lint Netlist
3+ yrs exp
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ASIC Design and Integration Engineer, Silicon Security

Apple Inc

Cupertino, CA 38 days ago $129,300–$194,700
Actively hiring Confirmed live yesterday Trusted Below market
RTL Verilog SystemVerilog ASIC Design CDC RDC UPF Synthesis Timing Closure AMBA AXI AHB APB Cryptography Low-power Design Lint Netlist Hardware Security
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ASIC Design Engineer, IP Integration & Implementation

Apple Inc

Sunnyvale, CA 44 days ago $184,700–$324,800
Actively hiring Confirmed live 2 days ago Trusted Above market
RTL ASIC Design AMBA AXI AHB APB UPF Python Perl TCL Logic Synthesis Static Timing Analysis Formal Verification Floorplanning Timing Closure Low-Power Design FPGA
10+ yrs exp
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PLL Design Integration Staff Engineer

Amd

San Jose, CA 45 days ago $166,400–$249,600
Actively hiring Confirmed live 2 days ago High trust Competitive pay
PLL FPGA IC Design Analog/Mixed-Signal VCO LDO Phase Interpolators SystemVerilog Vivado Clock Synthesis Digital Verification Post-Silicon Validation Floor Planning
Hybrid
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ASIC Design and Integration Engineer

Apple Inc

Cupertino, CA 144 days ago $184,700–$324,800
Actively hiring Confirmed live yesterday Low trust Above market
SystemVerilog RTL Design ASIC Design Synthesis Timing Analysis Power Optimization PCIe FPGA Prototyping CDC RDC LINT LEC High-speed I/O Formal Verification Simulation
10+ yrs exp
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ASIC Design and Integration Engineer

Apple Inc

Beaverton, OR 144 days ago
Actively hiring Confirmed live yesterday Low trust
SystemVerilog RTL Design ASIC Design Synthesis Timing Analysis Power Optimization PCIe FPGA Prototyping CDC RDC LINT LEC High-speed I/O Formal Verification
10+ yrs exp
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ASIC Design and Integration Engineer

Apple Inc

Beaverton, OR 144 days ago
Actively hiring Confirmed live 2 days ago Low trust
SystemVerilog RTL Design ASIC Design Synthesis Timing Analysis Power Optimization Formal Verification High-speed I/O PCIe FPGA Prototyping CDC RDC LINT LEC Low-power Design
3+ yrs exp
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Integration RTL Design Engineer

Amd

San Jose, CA 169 days ago $166,400–$249,600
Actively hiring Confirmed live yesterday High trust Competitive pay
Verilog RTL Design ASIC SoC STA SDC PrimeTime Tempus AMBA AXI AHB APB PCIe CXL Python Perl Tcl DFT Low-Power Design
Hybrid
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