below marketmost similar roles pay hereabove market
This role pays more than
82%
of similar roles. Most pay
$177,250–$236,487
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At the midpoint, this role pays about
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versus about
$207k
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Based on 240 similar postings.
Employer
About Qualcomm
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has
575 open roles
on FindRole.
Listed pay typically runs
$147,900–$221,900
across 550 roles with salary data.
JOB TITLE: GPU Design Integration Engineer
The GPU Design Integration Engineer joins the GPU ASICS Engineering team to develop advanced graphics processors for various applications ranging from wearables to laptops. This role involves the architecture and micro-architecture of integration related IP, RTL design, synthesis, logic and timing verification, and the integration of complex IP to form a complete GPU. The engineer will work on 2D and 3D graphics, streaming processors, and high-speed IO interface and bus protocols. Key technical requirements include expertise in SystemVerilog, Logic design, and multi-clock design concepts. Candidates must demonstrate proficiency in functional ECO implementation, synthesis, and timing concepts. Preferred skills include familiarity with AMBA protocols like AXI, AHB, and APB, as well as Python scripting for automation and low power design.
Design the architecture and micro-architecture of integration-related IP.
Perform RTL design and synthesis for GPU components.
Execute logic and timing verification for complex IP blocks.
Integrate complex IP to form a complete, high-performance GPU.
Qualify RTL using frontend design tools such as Lint and CDC.
Implement functional ECOs to resolve design issues.
Manage multi-clock design concepts and timing for ASICs.
What we're looking for
Bachelor's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, or related work experience.
Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 5+ years of Software, Hardware, or Systems Engineering experience.
PhD in Computer Engineering, Computer Science, Electrical Engineering, or related field and 4+ years of Software, Hardware, or Systems Engineering experience.
Strong design experience with SoC and/or IP level integration of design blocks.
RTL expertise in SystemVerilog with the ability to qualify RTL using Lint and CDC tools.
Experience in logic design, micro-architecture, RTL coding, and functional ECO implementation.
Strong understanding of multi-clock design concepts, synthesis, and ASIC timing concepts.
Familiarity with AMBA protocols, Python scripting, GPU/multimedia IP development, and low power design (preferred).
ASIC Implementation
Physical Design
Place and Route
PPA Optimization
Synthesis
DFT
Floorplanning
TCL
Perl
Python
RTL
Power Distribution
Physical Signoff
Design for Yield
Thermal Management
multi Vt
ASIC Implementation
Physical Design
Place and Route
Synthesis
DFT
Floorplanning
PPA Optimization
TCL
Perl
Python
RTL
Clock and Power Distribution
Physical Signoff
Design for Yield
Thermal Management
multi Vt
Physical Design
ASIC Implementation
Place and Route
Floorplanning
Synthesis
DFT
Clock and Power Distribution
RTL
Multi-voltage
Power Retention
Design for Yield
Manufacturability
Thermal Management
Tapeout
ASIC Implementation
Physical Design
Place and Route
Floorplanning
Synthesis
DFT
Clock and Power Distribution
RTL
Multi-voltage
Power Retention
Design for Yield
Manufacturability
Thermal Management
Hierarchical Design
Top-down Design