GPU Design Integration Engineer

Qualcomm

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$195,200–$292,800 / yr
Posted
10 days ago
Freshness
Confirmed live yesterday
Closes
Feb 28, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $200k
This role $244k
$134k most similar roles pay here $310k

This role pays more than 83% of similar roles. Most pay $164,437–$235,750 — the shaded band above. At the midpoint, this role pays about $244k versus about $200k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · GPU Design Integration Engineer

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The GPU Design Integration Engineer joins the GPU ASICS Engineering team to develop high-performance graphics processors for a wide range of applications including wearables and laptops. This role focuses on the architecture and micro-architecture of integration related IP, performing RTL design, synthesis, logic and timing verification, and the integration of complex IP to form complete GPUs. The work involves solving technical challenges in 2D and 3D graphics, streaming processors, and high-speed IO interface and bus protocols. Candidates must possess expertise in SystemVerilog for RTL coding, multi-clock design concepts, functional ECO implementation, and synthesis timing. Preferred skills include familiarity with AMBA protocols like AXI, AHB, and APB, as well as Python scripting for automation and low power design experience. The role requires coordinating across software, power, and design teams to deliver integrated multimedia ICs.

Skills

ASIC RTL Design SystemVerilog Synthesis Logic Design Micro-architecture AMBA AXI AHB APB Python Low Power Design CDC Lint

What you'll do

  • Design the architecture and micro-architecture of integration-related IP for GPU systems.
  • Perform RTL design and coding using SystemVerilog for complex integrated components.
  • Execute logic and timing verification to ensure high-performance chip functionality.
  • Integrate complex IP blocks to form a complete, functional GPU.
  • Qualify RTL designs using frontend tools such as Lint and CDC.
  • Implement functional ECOs and manage synthesis processes for ASIC production.
  • Manage multi-clock design concepts and low-power design requirements.
  • Develop scripts in Python to automate internal design and verification workflows.

What we're looking for

  • Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or a related field.
  • Master's degree with 5+ years of experience in Software, Hardware, or Systems Engineering.
  • PhD with 4+ years of experience in Software, Hardware, or Systems Engineering.
  • At least 5 years of ASIC design, verification, or related work experience.
  • Expertise in RTL coding using SystemVerilog and ability to qualify RTL with Lint and CDC tools.
  • Experience in logic design, micro-architecture, synthesis, and understanding timing concepts for ASICs.
  • Familiarity with AMBA protocols (AXI, AHB, APB) and low power design.
  • Proficiency in scripting languages such as Python to improve automation.

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