This role pays less than
86%
of similar roles. Most pay
$162,000–$231,300
— the shaded band above.
At the midpoint, this role pays about
$152k
versus about
$197k
for comparable roles.
Based on 240 similar postings.
Employer
About Qualcomm
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has
568 open roles
on FindRole.
Listed pay typically runs
$150,615–$222,050
across 554 roles with salary data.
The SoC Design and Integration Engineer joins a fast-paced team responsible for RTL design, flows, and methodology for high-performance ASICs on advanced process nodes. This role focuses on the High Performance Compute and AI spaces, where the engineer will oversee the definition, design, verification, and documentation of ASIC development for various products. Daily responsibilities include executing architecture and design according to protocols, resolving complex verification problems using sound engineering practices, and determining architecture designs and large-scale system simulations. The candidate must possess expertise in Server and Data Center IPs, protocols, and interfaces, alongside experience designing arithmetic, computational, or machine learning IPs. Key technical skills include a deep understanding of speed and power efficiency design techniques, along with the ability to develop tools and scripting for process automation.
Execute the architecture and design of SoCs according to provided design protocols.
Resolve complex architecture, design, and verification problems using established ASIC engineering practices.
Execute design and verification strategies for ASICs, SoC, and IP cores based on specific requirements.
Design arithmetic, computational, and machine learning IPs for high-performance computing.
Determine architecture designs, logic designs, large-scale integration, and system simulations.
Identify areas for flow and process improvements through advanced design techniques and automation.
Develop tools and scripts to automate internal processes.
Provide feedback on silicon learnings to the process team regarding methodology and IP design.
What we're looking for
Bachelor's degree in Science, Engineering, or related field with 2+ years of ASIC experience, a Master's with 1+ year, or a PhD.
Proven knowledge in Server/Data Center IPs, protocols, and interfaces.
Experience designing arithmetic, computational, or machine learning IPs (preferred).
Strong understanding of design techniques for speed and power efficiency.
Ability to oversee definition, design, verification, and documentation for ASIC development.
Ability to determine architecture design, logic design, large-scale integration, and system simulation.
Experience developing tools and scripting for process automation (preferred).
Master's degree in Electrical Engineering, Computer Science, or Computer Engineering (preferred); 5+ years of experience in ASIC design, scripting, and architecture (preferred).