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ASIC Design RTL Synthesis Static Timing Analysis Physical Design Power Analysis Python TCL EDA Tools VLSI PPA Optimization Formal Verification AI Agents LLM Data Analytics Design Infrastructure DFT +11 more Show less

Network Engineering BGP OSPF TCP/IP VLAN VPN VRF DNS DHCP ISIS Router Firewall Load Balancer SharePoint ITIL Security+ CCNA CCNP MCSE CISSP Change Management WAN +17 more Show less

Network Engineering BGP OSPF TCP/IP VLAN VPN VRF DNS DHCP ISIS Router Firewall Load Balancer SharePoint Change Management ITIL Security+ CCNA CCNP CISSP WAN Circuit Configuration Multiplexers +18 more Show less

Azure Salesforce TSQL DB Design Software Configuration Troubleshooting Enterprise Software Case Management +3 more Show less

System Design System Implementation TCP/IP LTE Technical Writing Radio Voice Communications CJIS) Security Policy Digital Evidence Management Public Safety Software +4 more Show less

Place and Route Timing Closure STA Floor-planning Clock Tree Synthesis Physical Verification LVS DRC Equivalence Checks Power Optimization ECO ICC2 Innovus Primetime Caliber LEC SoC Design +12 more Show less

SaaS C# Java Python JavaScript MSSQL Oracle MySQL APIs System Integrations Agile Root-Cause Analysis Technical Documentation Scripting Automation +10 more Show less

Networking Telecommunications DWDM Ethernet IP-VPN Dark Fiber DIA Broadband Cellular Satellite Cloud Connectivity AWS Azure Jira Confluence AI Automation +12 more Show less

API Golang Software Development Technical Design Deployment Integration Finxact Core APIs +2 more Show less

ASIC Implementation Synthesis Physical Design UPF RTL Netlist DFT P&R LEC CMOS DFM Power Gating +7 more Show less

RTL Synthesis place-and-route Static Timing Analysis STA floor-planning PPA DRC LVS ECO Power Intent Validation IR Drop EMIR +8 more Show less

Synthesis RTL-to-gate synthesis QoR Synopsys Fusion Compiler Cadence Genus Python Perl Tcl Make Timing Analysis Place-and-Route Floorplanning Power Planning Routing Timing Closure Physical Design +11 more Show less

RTL-to-GDSII STA DFT UPF Tcl Python Perl Shell Make Clock Tree Synthesis Floorplanning Power Delivery Network Physical Verification Signoff Synthesis +10 more Show less

SaaS MSSQL Oracle MySQL APIs C# Java Python JavaScript System Integration Troubleshooting Technical Documentation Data Exchange Digital Banking +9 more Show less

RTL Synthesis place-and-route Static Timing Analysis STA PPA floor-planning LVS DRC ECO Power Intent Validation IR Drop EMIR Microarchitecture Physical Design Logic Equivalence Timing Closure +12 more Show less

Physical Design STA CMOS Circuit Design Perl TCL Spice Formal Verification Physical Verification DFM SoC Design Computer Architecture Layout Design Clock Analysis Low Power Design +9 more Show less

RTL Synthesis UPF Low Power Design Logical Equivalence Lint ECO Python Perl Tcl ASIC SOC Design Power Intent Verification +8 more Show less

Synthesis PNR VLSI Python TCL STA SAPR Physical Design Logic Optimization PPA Scripting Algorithms +7 more Show less

RTL-to-GDS Synthesis place-and-route PnR PPA Optimization CPU Microarchitecture Clock Flow Physical Design Memory Design Process Technology Evaluation +5 more Show less

RTL Synthesis UPF Low Power Design Logical Equivalence Lint ECO Python Perl Tcl ASIC SOC Design Power Intent Verification +8 more Show less