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EC2 EBS ELB S3 RDS Windows Linux NDR EDR NGFW IDS IPS F5 Cybersecurity Cloud Infrastructure Architecture Diagrams +11 more Show less

Physical Design Synthesis PnR STA CTS Floorplanning Routing UPF Python Tcl Innovus ICC2 Fusion Compiler Genus PrimeTime Tempus LEC VLSI +13 more Show less

C# Java Python JavaScript MSSQL Oracle MySQL Scripting Troubleshooting +4 more Show less

RTL ASIC Design AMBA AXI AHB APB UPF Python Perl TCL Logic Synthesis Static Timing Analysis Formal Verification Floorplanning Timing Closure Low-Power Design +11 more Show less

RTL ASIC Design Synthesis Physical Design Synopsys Conformal LEC Synopsys Formality Synopsys PrimeTime Tcl Perl Python VLSI CMOS PPA Tape-out FINFET GAA +12 more Show less

Windows Networking Wi-Fi Bluetooth SQL Server Active Directory VMware Azure Scripting VLANs Subnets Firewalls Encryption Device Imaging +9 more Show less

Power Analysis RTL Synthesis System Verilog Static Timing Analysis Formal Verification TCL Python Perl Linux Power Artist PrimetimePX Clock Gating Power Gating Multi VT Design SoC Design Thermal Analysis +12 more Show less

MSSQL Oracle MySQL APIs C# Java Python JavaScript SaaS System Integration Troubleshooting Technical Documentation Data Exchange +8 more Show less

AI/ML HPC Azure Python CI/CD Data Lakes RAG Agentic Workflows Systems Engineering Configuration Management GPU Resources SPDM CFD MBSE +9 more Show less

Physical Design CAD Python Tcl Shell Synthesis place-and-route Static Timing Analysis Power Optimization Cadence Synopsys Calibre ICV DTCO PPA SoC GPU +12 more Show less

STA Primetime Fishtail TCM Tcl Perl Python ASIC Design Timing Closure Power Analysis RTL Design Physical Design Multi-voltage Domain Crossing Clock Domain Crossing Synthesis +10 more Show less

RTL ASIC Design AMBA AXI AHB APB UPF Python Perl TCL Logic Synthesis Static Timing Analysis Formal Verification Floorplanning Timing Closure Low-Power Design FPGA +12 more Show less

TCP/IP LTE Router Modem System Design Technical Writing Radio Voice Communications Digital Evidence Management +3 more Show less

ASIC SoC Design RTL to GDS Flow Python Ruby Perl Tcl Make Perforce Git Artifactory Linux Unix AI Tools +9 more Show less

Physical Design Floorplanning DRC LVS EMIR Python Tcl Perl EDA Tools Switch Fabric DDR SerDes HBM Chiplet Power Grid Design Multi-voltage Domain +11 more Show less

STA SDC Tcl Python Perl Shell ASIC MMMC Cadence Synopsys Signal Integrity IR-drop DFT PVT ATPG MBIST +11 more Show less

Static Timing Analysis Digital Synthesis VLSI Synopsys Design Compiler Cadence Genus TCL Python Perl Logic Equivalency Check ASIC SoC EDA Tools +7 more Show less

Verilog System-Verilog RTL Design ASIC Design Flow Synthesis Static Timing Analysis Formal Verification Physical Design ECO UPF CPF CDC RDC Synopsys Design Compiler Conformal LEC Synopsys Formality Synopsys PrimeTime UNIX Perl TCL Shell Scripting +16 more Show less

Physical Design Floorplanning DRC LVS EMIR Python Tcl Perl EDA Tools High Speed DDR SerDes HBM D2D I/O Chiplet Power Grid Design Multi-voltage Domain Bump Planning +12 more Show less

RTL2GDS Synthesis place-and-route CTS Python TCL Perl Make Synopsys Cadence DFT Floorplanning PPA Optimization AI/ML UPF CPF +11 more Show less