Senior Implementation Engineer

Amazon Inc

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Quick summary

Work type: On-site
Location: Sunnyvale, CASan Diego, CA
Salary: $185,200–$250,000 / yr
Posted: 3 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $182k

This role $218k

$132k $263k

below market most similar roles pay here above market

This role pays more than 94% of similar roles. Most pay $169,050–$195,887 — the blue band above. At the midpoint, this role pays about $218k versus about $182k for comparable roles.

Based on 240 similar postings.

Employer

About Amazon Inc

Amazon Inc. is the world''s largest e-commerce and cloud computing company, operating the Amazon marketplace, AWS cloud platform, Prime subscription services, Alexa voice AI, and logistics infrastructure. Industry: E-Commerce & Cloud Computing

Amazon Inc currently has 647 open roles on FindRole.

Listed pay typically runs $143,700–$194,400 across 645 roles with salary data.

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At a glance

TL;DR · Senior Implementation Engineer

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Sr. Implementation Engineer, Amazon Leo joins the Amazon Leo team to develop digital chip SOCs for communications via Low Earth Orbit satellites and gateways. This role involves defining and implementing wireless solutions, including modems, high-speed interfaces, embedded processors, and DSP solutions using latest CMOS generation technologies. Key responsibilities include developing chip power intent using UPF, setting up logic and physical synthesis flows, and creating timing constraints. The engineer will perform STA and LEC on netlists, conduct formal connectivity checks for analog blocks, and lead timing sign-off for post-P&R databases. Required skills include ASIC implementation experience for deep sub-micron nodes, physical synthesis methodology development, and familiarity with power gating. The work addresses the technical challenge of providing low-latency, high-speed broadband connectivity to underserved communities.

Skills

ASIC Implementation Synthesis Physical Design UPF RTL Netlist DFT P&R LEC CMOS DFM Power Gating

What you'll do

Develop chip power intent using UPF and validate it at the RTL and netlist levels.
Establish logic and physical synthesis flows for various technology nodes.
Create timing constraints by analyzing the design with ASIC and DFT teams.
Perform Static Timing Analysis (STA) and Logic Equivalence Checking (LEC) on netlists.
Verify top-level integration of analog blocks and perform formal connectivity checks.
Manage netlist hand-offs to P&R teams and oversee the execution of physical design tasks.
Lead timing sign-off for the post-P&R database to ensure performance targets.
Verify IR/EM results to ensure the chip meets required Design for Manufacturing (DFM) criteria.

What we're looking for

Bachelor's degree in Electrical Engineering or a related field.
8+ years of experience in ASIC implementation, including synthesis, STA, and P&R for deep sub-micron nodes (preferably 16nm or smaller).
Experience leading or solely developing methodology and scripts for physical synthesis.
Proven track record of taping out chips for high volume production.
Familiarity with implementing chips with multiple power islands and power gating.
Master's or Ph.D. degree in Electrical or Communications Engineering (preferred).
10+ years of experience in ASIC implementation (preferred).
Export control laws and regulations, candidates.