CPU Implementation Engineer

Apple Inc

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Quick summary

Work type: On-site
Location: Austin, TX
Posted: 15 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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How this pay compares to similar roles

Similar $220k

$137k most similar roles pay here $288k

This listing doesn't post a salary. Most similar roles pay $184,900–$254,750.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3553 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2740 roles with salary data.

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At a glance

TL;DR · CPU Implementation Engineer

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As a CPU Implementation Engineer, you will work extensively with micro-architects to define micro-architecture and perform design feasibility while managing power, performance, and area trade-offs. Your daily responsibilities involve driving RTL-to-GDS design convergence through logic optimizations using synthesis and place-and-route tools. You will manage block-level delivery, backend flow closure, electrical requirements, and silicon yield improvements. Collaborating with internal CAD and PD methodology teams, you will utilize industry standard synthesis and PNR tool features to optimize CPU designs. You will also coordinate with cross-functional teams on floorplanning, timing, power, reliability, and testability while co-optimizing memory macros and library standard cells with custom IP teams. Key technical tasks include implementing structured data-path designs, performing Static Timing Analysis for multi-GHz designs, executing ECO methodologies to resolve noise or EMIR problems, and ensuring zero LVS and DRC violations.

Skills

RTL Synthesis Place-and-Route Static Timing Analysis STA floor-planning IR Drop EMIR LVS DRC ECO PPA

What you'll do

Define micro-architecture and perform PPA trade-offs with micro-architects.
Drive RTL-to-GDS design convergence through synthesis and place-and-route optimizations.
Implement structured data-path designs while maintaining logic equivalence and timing closure.
Generate comprehensive timing constraints for multi-GHz designs to reduce iteration cycles.
Execute floor-planning strategies including macro positioning and power grid distribution.
Apply advanced place-and-route techniques to resolve critical path timing and power issues.
Develop and execute ECO methodologies to resolve timing, noise, and EMIR problems.
Manage physical design verification flows to ensure zero LVS and DRC violations.

What we're looking for

Master's degree or foreign equivalent in Electrical and Computer Engineering or a related field.
Experience designing and optimizing CPU micro-architectures in collaboration with RTL teams.
Ability to analyze trade-offs for CPU features across performance, area, timing, power, and complexity metrics.
Experience implementing structured data-path designs using industry-standard synthesis flows and performing Static Timing Analysis.
Experience generating comprehensive timing constraints for multi-GHz designs using synthesis, PnR, and STA tools.
Experience executing floor-planning strategies including hierarchical pin placement, macro positioning, and power grid distribution.
Expertise in advanced place-and-route techniques to achieve timing closure and optimize power density.
Ability to develop and execute ECO methodologies to resolve timing violations, noise issues, and EMIR problems.