Staff Implementation Engineer

Arm Holdings

Confirmed live today High trust

Quick summary

Work type: On-site
Location: Austin, TX
Salary: $198,100–$268,000 / yr
Posted: 1 day ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $211k

This role $233k

$150k most similar roles pay here $281k

This role pays more than 67% of similar roles. Most pay $182,000–$240,887 — the shaded band above. At the midpoint, this role pays about $233k versus about $211k for comparable roles.

Based on 240 similar postings.

Employer

About Arm Holdings

Arm Holdings plc is a leading British semiconductor and software design firm, established in 1990 and recognized for developing energy-efficient processor architectures that power nearly all smartphones and a vast range of IoT and computing devices.

Arm Holdings currently has 109 open roles on FindRole.

Listed pay typically runs $209,100–$282,900 across 108 roles with salary data.

Most-posted roles

View all roles at Arm Holdings

At a glance

TL;DR · Staff Implementation Engineer

Role Posting Log in to save

As a Staff Implementation Engineer in the Solutions Engineering group, you will drive the end-to-end RTL-to-GDSII physical implementation of sophisticated CPU, GPU, interconnect, and SoC designs through tapeout. You will be responsible for managing timing closure across MCMM scenarios, including setup, hold, and clocking, while ensuring signoff for STA, physical verification, and power integrity. Your daily work involves collaborating with RTL and architecture teams to translate PPA requirements into implementation targets, debugging complex EDA-tool issues, and developing automation scripts using Tcl, Python, Perl, shell, or Make. You will navigate technical challenges such as floorplanning, placement, clock tree synthesis, and low-power design involving UPF and multiple voltage domains. This role focuses on the physical build of high-performance processor cores and communication fabrics across advanced nodes to solve complex hardware integration problems.

Skills

RTL-to-GDSII Physical Design STA DFT UPF Tcl Python Perl Shell Make Synthesis Floorplanning Clock Tree Synthesis Power Delivery Network Signoff SoC

What you'll do

Drive end-to-end RTL-to-GDSII physical implementation for processor cores, graphics units, and SoC builds through tapeout.
Execute timing closure across MCMM scenarios including setup, hold, clocking, and complex path analysis.
Manage physical implementation readiness across STA, physical verification, power integrity, and other signoff requirements.
Coordinate with DFT teams to ensure scan, test modes, and other requirements are correctly implemented.
Debug complex implementation and EDA-tool issues by working directly with vendors and internal methodology teams.
Identify project risks early and develop mitigation plans to ensure successful tapeout.
Develop and improve implementation methodologies, automation scripts, and flows to increase design quality.

What we're looking for

Bachelor's degree or equivalent experience in Electrical Engineering, Computer Engineering, or a related technical field.
10+ years of hands-on ASIC Physical Build/Implementation experience from RTL to GDSII with successful tapeout.
Expertise in the full implementation lifecycle including synthesis, floorplanning, PDN planning, placement, CTS, and routing.
Proficiency in MCMM timing closure, OCV methodologies, and advanced-node timing challenges.
In-depth knowledge of low-power implementation techniques such as UPF, multi-voltage domains, and power gating.
Strong scripting and automation skills using Tcl, Python, Perl, shell, and/or Make.
Experience implementing high-performance Arm CPUs, GPUs, coherent interconnects, or complex SoCs (preferred).
Familiarity with sophisticated process nodes, hierarchical physical design, and structured clock architectures (preferred).

Save