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UVM C Verilog SystemVerilog Python Docker CI/CD Kubernetes AWS Azure PostgreSQL Git Jenkins Prometheus Grafana +10 more Show less

UVM SystemVerilog Verilog PCIe NVMe RDMA Python CI/CD Kubernetes AWS GitHub JIRA PostgreSQL Mentor Graphics Questa Simulator Cadence Incisive Verilog Simulator +10 more Show less

CREO Windchill GD&T Zuken Military and aerospace specifications Microsoft Office AutoCAD +2 more Show less

SiemensNX TeamCenter Ansys GD&T JIRA Confluence PCBA CAD DFA DFM Fiber-opticHandling AgileMethodology +7 more Show less

STA EDA tools Timing Constraints Synthesis Equivalence Checking Floor-planning Physical Design Deep Sub-micron Process Nodes AI/LLM Python C++ Perl Tcl Shell Scripting +9 more Show less

Verilog Python RTL ASIC VLSI Digital systems Computer Architecture Computer Arithmetic RAG pipelines Vector databases LLM fine-tuning Multi-agent systems CI/CD +8 more Show less

SystemVerilog UVM Perl Python PCIe CXL Ethernet AHB AXI DDR MMU Veloce HAPS FormalVerification iEV VC Formal +11 more Show less

Innovus Tempus Redhawk Voltus Calibre Python TCL Perl RTL2GDSII Hierarchical_Floorplanning Place_and_Route Static_Timing_Analysis Power_Integrity Equivalence_Checks Clock_Tree_Synthesis STA_setup Timing_Methodologies ECO_Implementation Functional_ECO Timing_ECO Automation Tapeouts 7nm 5nm 3nm +20 more Show less

ASIC Verilog SystemC Python Perl C++ Linux Git JIRA Confluence CI/CD +6 more Show less

Tcl Python Perl Cadence Synopsys ASIC STA SDC On-Chip_Variation Signal_Integrity IR-drop_aware_STA MMMC_Analysis ECOs RTL Physical_Design DFT Power_Performance_Area_Tradeoffs EDA_Tools +13 more Show less

Virtuoso RTL to GDS Flow SystemVerilog Python Perl C++ TCL UVM DVFlow CI/CD Linux Git SVN DOCSIS Moore's Law Mentor Graphics Calibre Cadence Virtuoso Synopsys IC Compiler Synopsys PrimeTime Qualcomm SNAP EDA Suite +15 more Show less

C/C++ UVM System C DPI-C Matlab

UVM SystemVerilog C Matlab Python DPI-C SystemC Formal verification Verilog VCS DVflow CI/CD +7 more Show less

Python Labview C/C++ NI dSPACE GEVS SMC-S-016 FPGA SOC Automated test systems Calibration procedures Oscilloscopes Multimeters Switching power supplies Electric motors IMUs Sensors RF +13 more Show less

RTL Verilog SystemVerilog VHDL SoC IP integration Ethernet SERDES LPDDR5/6X Arm CPU 3rd party IP blocks low power design DFT synthesis STA physical design deep sub-micron nodes communication systems wireless communications serial protocols SPI I2C I3C UART +19 more Show less

SiemensNX TeamCenter Ansys JIRA Confluence CAD DFM DFA Agile 3DDesign MechanicalEngineering FiniteElementAnalysis ProjectManagementSoftware ManufacturingProcessDevelopment SpaceSystemsDesign TestCampaignsDesign TechnicalDocumentation InterdisciplinaryCollaboration +13 more Show less

UVM Matlab SystemC DPI-C Verilog VHDL RTL Python CI/CD AWS Linux Git SVN JIRA Confluence +10 more Show less

UVM SystemVerilog C SystemC DPI-C Matlab +1 more Show less

MATLAB UVM SystemC DPI-C RTL DSP Verilog VHDL Linux Python Git CI/CD ASIC FPGA Simulation Verification Power Optimization Timing Optimization +13 more Show less

RTL UVM SystemC DPI-C DSP MATLAB Verilog VHDL ASIC CMOS Linux Git CI/CD Python PostgreSQL +10 more Show less