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Innovus Primetime Voltus Synopsys ICC Tcl Python Perl Physical Design EMIR Timing Closure Floorplanning Place and Route DRC +8 more Show less

Verilog System Verilog UVM Python Perl Palladium Protium Zebu Veloce C-DPI System Verilog Assertions Emulation Mixed Signal Splunk +9 more Show less

System Verilog Verilog UVM RTL SoC Verdi Digital Design Functional Coverage Computer Architecture Logic Design +5 more Show less

Cadence-Innovus Physical Design Place and Route TCL Python floor planning Low Power Design Clock Gating Power Gating Design for Yield Manufacturability +6 more Show less

System Verilog UVM Python Perl RTL SoC Verification Functional Coverage Computer Architecture Digital Design Constrained Random Verification +5 more Show less

PnR STA Tcl Shell Scripting DRC LVS Power Grid Design Physical Design EDA Tools +4 more Show less

Physical Design PnR STA DRC LVS TCL Shell Scripting Power Grid Design IR Drop Electromigration +5 more Show less

System Verilog UVM Python Perl C++ NCSIM Xcelium RTL Digital Design PCI Express DisplayPort MIPI Functional Coverage Code Coverage Assertions Hardware Security Memory Management Unit Power Management Fabric Infrastructure +14 more Show less

System Verilog Verilog Python C C++ VLSI Design RTL SoC Firmware UPF ATE Digital Design Analog Co-simulation +8 more Show less

SystemVerilog RTL Verification Hardware Description Language PCB Design Lab Instrument Automation Test Coverage Synthesis Simulation +4 more Show less

Innovus Fusion Compiler Physical Design Static Timing Analysis TCL Python Perl floor planning Clock Tree Synthesis Routing ECO CMOS IR/IVD Analysis Power Gating Clock Gating Multi-voltage Domain DRC LVC +13 more Show less

DRC LVS Cadence Virtuoso Cadence Innovus Tcl Python Perl CMOS Layout PnR APR RDL Physical Verification tape out +8 more Show less

SystemVerilog Python Perl Tcl C++ C Assembly Jasper RTL Formal Verification VLSI Design CMOS Makefile Functional Coverage Digital Logic Computer Architecture +11 more Show less

SystemVerilog UVM Formal Verification Python Perl Tcl Cadence Xcelium VManager Virtuoso Jasper Gold Verdi VLSI EDA Tools +8 more Show less

PnR ICC2 Innovus PrimeTime TCL Python Perl Unix EMIR Voltus Redhawk Calibre floor planning Timing Closure Scripting +10 more Show less

RFIC mm-Wave Analog Circuit Design Mixed-Signal Design HFSS EMX FinFET SOI BiCMOS Bulk CMOS 4G 5G NR WiMAX 802.11ad Network Analyzers Spectrum Analyzers Oscilloscopes +12 more Show less

Python C++ VLSI EDA AI LLMs Signal Integrity Power Delivery Parasitic Extraction IC Physical Design Data Structures Algorithms Object-Oriented Design +8 more Show less

Physical Design VLSI RTL2GDS Timing Closure Power and Clock Distribution IR Drop Analysis RC Extraction Synopsys (ICC2 Cadence (Genus Python Perl Tcl Make +8 more Show less

Synthesis RTL-to-gate synthesis QoR Synopsys Fusion Compiler Cadence Genus Python Perl Tcl Make Floorplanning Power Planning Routing Timing Closure Place-and-Route Flow Physical Design +10 more Show less

Verilog Python Perl Unix Linux Makefiles ASIC Verification RTL Generation DevOps Synthesis CDC Digital Design Hardware Design +8 more Show less