ASIC Physical Design and Timing Engineer, New College Grad 2026

Nvidia

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$116,000–$189,750 / yr
Posted
2 days ago
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $185k
This role $153k
$104k most similar roles pay here $231k

This role pays less than 77% of similar roles. Most pay $157,937–$212,500 — the shaded band above. At the midpoint, this role pays about $153k versus about $185k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 964 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 953 roles with salary data.

Most-posted roles

View all roles at Nvidia

At a glance

TL;DR · ASIC Physical Design and Timing Engineer, New College Grad 2026

Role Posting Log in to save

Join our dynamic team as an ASIC Timing Engineer where you will drive the physical design and timing analysis of NVIDIA’s GPUs, CPUs, DPUs, and SoCs at various levels, from block to full chip. You’ll play a pivotal role in frontend and backend implementation, including synthesis, equivalence checking, floor-planning, and ECO implementation, ensuring timing and power convergence. This position requires expertise in static timing analysis (STA) and proficiency with industry-standard EDA tools. Ideal candidates have a master’s degree or higher in Electrical or Computer Engineering, hands-on experience in full-chip/sub-chip STA, and knowledge of deep sub-micron process nodes. Experience in AI/LLM and programming languages is beneficial, as you will contribute to the advancement of cutting-edge technology at NVIDIA.

Skills

STA EDA tools Timing Constraints Synthesis Equivalence Checking Floor-planning Physical Design Deep Sub-micron Process Nodes AI/LLM Python C++ Perl Tcl Shell Scripting

What you'll do

  • Drive physical design and timing analysis for NVIDIA's GPUs, CPUs, DPUs, and SoCs at various levels.
  • Manage frontend and backend implementation including synthesis, equivalence checking, and ECO implementation.
  • Ensure timing and power convergence throughout the chip development process.
  • Generate and manage timing constraints to optimize performance and efficiency.
  • Collaborate with cross-functional teams to advance innovative projects.

What we're looking for

  • Master's degree or higher in Electrical or Computer Engineering.
  • Expertise in Timing and Static Timing Analysis (STA).
  • Hands-on experience with full-chip/sub-chip STA and timing convergence.
  • Proficiency in industry-standard EDA tools for timing analysis.
  • Proven experience in timing convergence for ASICs, CPUs, GPUs.
  • Knowledge of deep sub-micron process nodes.
  • Experience in physical design optimization techniques.

Related searches

More ASIC Physical Design and Timing Engineer jobs ASIC Physical Design and Timing Engineer jobs in Santa Clara All jobs at Nvidia

More like this

Similar roles

ASIC Physical Design Engineer, Netlisting

Nvidia

Santa Clara, CA +1 52 days ago $116,000–$189,750
Perl TCL Make Python Synopsys Cadence Logic Synthesis Equivalence Checking Formal Verification Clock Domain Crossing Checks MTBF Analysis RTL Design EDA Tools AI Utilization
Save

Senior ASIC Timing Engineer

Nvidia

Santa Clara, CA +3 6 days ago $136,000–$218,500
Static Timing Analysis Timing Constraints Generation ECOs Physical Design Optimization Synthesis Placement Routing Logic Restructuring STA Tools Deep Sub-Micron Process Nodes GPU STA CPU STA LPD STA SOC STA Logic Synthesis Equivalence Checking DFT Logic AMS Designs Methodology Development Flow Development Automation
Hybrid
Save

Senior ASIC Timing Engineer

Nvidia

Westford, MA +1 4 days ago $168,000–$264,500
Python Tcl Make Synopsys_PrimeTime Cadence_Tempus EDA_tools Static_Timing_Analysis Timing_Constraints_Generation ECOs Physical_Design_Optimization Logic_Synthesis Logical_Equivalence_Checking DFT_logic Deep_Sub_Micron_Technology Methodology_Development Automation
Save

Implementation Methodology Engineer

Nvidia

Santa Clara, CA 32 days ago $136,000–$218,500
Python Tcl Java C++ EDA tools logic design implementation physical design implementation synthesis formal-equivalence-checking flow automation physical synthesis placement routing logic restructuring
Hybrid
Save

Senior ASIC Physical Design Engineer, Netlisting

Nvidia

Santa Clara, CA +1 18 days ago $136,000–$218,500
Perl TCL Make Python RTL Logic Synthesis Static Timing Analysis Clock Domain Crossing Checking MTBF Analysis EDA Tools DFT Timing Closure Industry Standard EDA Tools Equivalence Checking/FV
Hybrid
Save