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ASIC Design RTL Synthesis Static Timing Analysis Physical Design Power Analysis Python TCL EDA Tools VLSI PPA Optimization Formal Verification AI Agents LLM Data Analytics Design Infrastructure DFT +11 more Show less

GPU Programming C++ Python HIP CUDA LLVM MLIR GPU Kernels Performance Analysis Quantized Models LLM Code-Generation System Software Development +8 more Show less

GPU Design Verification C++ Python SystemVerilog Verilog UVM Graphics Pipeline 3D Graphics Shaders Graphics APIs Formal Verification GPU Architecture +7 more Show less

SystemVerilog UVM C++ Python Perl GPU Design Verification Constrained-Random Testing Coverage-Driven Verification RTL Computer Architecture Hardware Modeling Emulation Performance Profiling Formal Verification +9 more Show less

Formal Verification SystemVerilog SystemVerilog Assertions (SVA) Python C/C++ Perl UVM Model Checking EDA Tools RTL Computer Architecture Graphics Pipelines UPF JIRA Confluence +10 more Show less

Verilog SystemVerilog RTL Design ASIC Design GPU Architecture Microarchitecture Synthesis Linting Timing Analysis SoC Hardware Design PPA Digital Design Cache Design Memory Systems Datapath Control Logic +12 more Show less

Verilog SystemVerilog RTL Design GPU Architecture SoC ASIC Design Flow Linting Synthesis Timing Analysis Microarchitecture PPA Digital Design Debug Simulation +9 more Show less

System Verilog Verilog UVM Python C++ ASIC Verification RTL Computer Architecture Testbench Development Regression Triage Coverage Closure Debug Caches Coherency Pipelines Arbitration Interconnect Networks Algorithms Data Structures +14 more Show less

Cadence-Innovus TCL Python Physical Design Place and Route STA Power Gating Clock Gating floor planning Design for Yield +5 more Show less

PCB Design OrCAD Allegro SiWave Simplis PSpice HSpice Schematic Capture Analog Circuit Modeling Control Theory Closed Loop Compensation Stability Analysis Oscilloscope Function Generator PMIC SVIx +11 more Show less

C C++ Python Verilog SystemVerilog Perl Matlab Vulkan UVM RTL ASIC SoC DSP LTE 5G Wi-Fi Linux Windows Machine Learning +14 more Show less

STA Timing Closure Physical Design RTL Synthesis DFT Clocking TCL Python Perl Shell Scripting ECO VLSI CMOS EDA Tools XALK POCVM ETMs +13 more Show less

Physical Verification DRC LVS ERC Calibre P&R Flows Floorplanning GPU Architecture Design for Yield Manufacturability ESD Multi Vt Strategies Global Timing Verification +8 more Show less

Physical Verification DRC ERC LVS Calibre P&R Flows Floorplanning ESD Design for Yield Manufacturability Multi Vt Strategies GPU Architecture Global Timing Verification Process ANT PERC +10 more Show less

ASIC Implementation Physical Design Place and Route PPA Optimization Synthesis DFT Floorplanning TCL Perl Python RTL Power Distribution Physical Signoff Design for Yield Thermal Management multi Vt +11 more Show less

ASIC Implementation Physical Design Place and Route Synthesis DFT Floorplanning PPA Optimization TCL Perl Python RTL Clock and Power Distribution Physical Signoff Design for Yield Thermal Management multi Vt +11 more Show less

UVM RTL Verification Formal Verification JasperGold OpenGL Metal Computer Architecture SoC Machine Learning Memory Sub-system Power Management +6 more Show less

SystemVerilog UVM Verilog RTL Verification Formal Verification JasperGold Scripting OpenGL Metal Computer Architecture Functional Coverage SoC Logic Simulators OOP +9 more Show less

SystemVerilog UVM Verilog RTL Verification Python Perl Ruby Formal Verification OpenGL Vulkan Metal Computer Architecture Logic Simulators Waveform Viewers SV Assertions +10 more Show less

ASIC Integration Physical Design Clock Distribution Floorplanning P&R Flows Timing Verification Netlist to Tapeout PPA ESD Solutions Design for Yield Manufacturability multi Vt strategies GPU Architecture +8 more Show less