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UVM SystemVerilog Verilog C C++ RTL GPU Architecture SystemC TLM Linux Perl Ruby Shell Scripting Makefiles ASIC Design Verification Simulation High-Level Synthesis +12 more Show less

ASIC RTL Design SystemVerilog Synthesis Logic Design Micro-architecture AMBA AXI AHB APB Python Low Power Design CDC Lint +9 more Show less

SystemVerilog C++ Python GPU Architecture RTL Constrained-Random Testing Functional Coverage Computer Architecture Graphics Pipelines 3D Graphics Verification Testbenches Semiconductor Design +7 more Show less

SystemVerilog UVM C++ Python Perl GPU Design Verification RTL Constrained-Random Testing Functional Coverage Computer Architecture Hardware Modeling Emulation Performance Profiling Coherent Interconnects +9 more Show less

Formal Verification SystemVerilog SVA Python C/C++ Perl UVM EDA Tools RTL Computer Architecture Graphics Pipelines Power Gating UPF JIRA Confluence Memory Subsystems +11 more Show less

RTL ASIC Design Synthesis Physical Design Synopsys Conformal LEC Synopsys Formality Synopsys PrimeTime Tcl Perl Python VLSI CMOS PPA Tape-out FINFET GAA +12 more Show less

PCB Design OrCAD Allegro PowerSI SiWave Simplis PSpice HSpice Control Theory Circuit Modeling High Frequency Magnetics Buck/Buck-Boost Regulators PWM Controllers LDOs PMICs Oscilloscope SVIx +12 more Show less

ASIC UVM SystemVerilog Verilog Python Perl VCS Verdi Xcelium Automation RTL Pre-silicon Verification Scripting Infrastructure Simulation Debug Metrics +12 more Show less

RTL Verilog SystemVerilog GPU SoC ASIC Synthesis Linting Timing Analysis PPA Microarchitecture Datapath Cache Design Memory Systems +9 more Show less

ASIC Verilog SystemVerilog C++ VCS Verdi Synopsys Micro-architecture Verification Methodologies Memory Coherency Arbitration Policies +6 more Show less

STA Timing Closure Physical Design RTL Synthesis DFT Clocking TCL Python Perl Shell Scripting EDA Tools VLSI ECO CMOS Digital Logic Design +11 more Show less

STA Timing Closure Physical Design TCL Python Perl Shell Scripting EDA Tools DFT Synthesis ECO Tapeout RTL Clocking OCV +10 more Show less

STA Timing Closure TCL Python Perl Shell Scripting EDA Tools DFT RTL Synthesis ECO PPA post silicon debug Tapeout OCV Cross-talk Clocking +12 more Show less

RTL Design Design Verification SystemVerilog Verilog ASIC GPU CPU Micro-architecture constrained‑random coverage‑driven verification PPA SoC tape‑out readiness +8 more Show less

Physical Design RTL Synthesis DFT Floorplanning Place and Route TCL Python Perl Shell Scripting VLSI CMOS EDA Tools Power Distribution Multi-voltage +10 more Show less

Physical Design PPA Optimization RTL Synthesis DFT Floorplanning Place and Route TCL Perl Python ASIC Multi-voltage Design for Yield Thermal Management Tapeout +10 more Show less

Physical Design ASIC RTL PPA Optimization Floorplanning Place and Route DFT Synthesis TCL Python Perl Multi-voltage Tapeout Design for Yield Thermal Management +10 more Show less

System Verilog Verilog UVM Python C++ ASIC Verification Pre-silicon Testbench Development Computer Architecture Arbitration Scripting Data Structures Algorithms RTL Performance Verification +10 more Show less

System Verilog UVM Verilog VHDL C C++ Python Vulkan FPGA Emulation Palladium Zebu QEMU Make Airflow GDB uboot UEFI +13 more Show less