GPU Physical Verification Design Engineer

Apple Inc

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Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$184,700–$324,800 / yr
Posted
15 days ago
Freshness
Confirmed live today

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $206k
This role $255k
$129k most similar roles pay here $346k

This role pays more than 97% of similar roles. Most pay $177,050–$235,562 — the shaded band above. At the midpoint, this role pays about $255k versus about $206k for comparable roles.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3513 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2730 roles with salary data.

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At a glance

TL;DR · GPU Physical Verification Design Engineer

As a GPU Physical Verification Design Engineer within the Silicon Technologies group, you will drive physical verification aspects throughout the design cycle for high-performance, power-efficient GPUs. You will work closely with the Physical Design team to establish methodologies, guidelines, and checklists while managing and resolving complex flow issues from early planning through tapeout. Your daily responsibilities include tracking progress, providing technical support, and collaborating with cross-functional teams to achieve back-end design goals. The role requires expertise in hierarchical top-down design, physical convergence, and specific checks including Base/Metal DRC, ERC, LVS, Process ANT, PERC, and ESD. You will utilize P&R flows and tools like Calibre while managing large subsystem designs exceeding 20M gates at frequencies over 1GHz. Key technical domains include multi-voltage and clock domains, mixed signal integration, and design for yield and manufacturability.

What you'll do

  • Execute physical verification closure from early design planning through tapeout.
  • Drive methodologies, guidelines, and checklists to streamline the physical design workflow.
  • Resolve complex design and flow issues related to physical design and large chip integration.
  • Perform Physical Verification checks including DRC, ERC, LVS, Process ANT, PERC, and ESD.
  • Integrate internal and external IP while specifying requirements in the physical domain.
  • Manage multi-voltage/clock domains, ESD solutions, and mixed-signal block integration.
  • Address design issues related to yield, manufacturability, multi-Vt strategies, and thermal management.
  • Utilize floorplanning tools and P&R flows to ensure global timing verification and physical closure.

What we're looking for

  • Bachelor of Science degree and 10 years of relevant experience.
  • Experience with hierarchical design approach, top-down design, budgeting, and physical convergence.
  • Experience with Physical Verification checks including Base/Metal DRC, ERC, LVS, Process ANT, PERC, and ESD.
  • Experience with P&R flows and Physical Verification tools such as Calibre.
  • Experience with Floorplanning tools, global timing verification, and Physical Design Verification Flows.
  • Experience integrating IP from internal and external vendors to specify and drive requirements in the physical domain (preferred).
  • Experience with Physical Design topics including multiple voltage/clock domains, ESD solutions, and mixed signal block integration (preferred).
  • Experience with large subsystem designs (>20M gates) at frequencies over 1GHz using new technologies (preferred).

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