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Active Keyword: DDR Design Engineer Remove filter Clear all

14 of up to 20 (filtered)

DDR Design Engineer

Apple Inc

15 days ago $175,000–$308,500
Actively hiring Confirmed live today High trust Above market
10+ yrs exp
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DDR Design Engineer

Apple Inc

15 days ago $184,700–$324,800
Actively hiring Confirmed live today High trust Above market
10+ yrs exp
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DDR Design Engineer

Apple Inc

15 days ago $165,800–$292,400
Actively hiring Confirmed live today High trust Above market
10+ yrs exp
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DDR Design Engineer

Apple Inc

Irvine, CA 15 days ago $175,000–$308,500
Actively hiring Confirmed live today High trust Above market
Verilog SystemVerilog RTL Design DDR PHY Logic Synthesis Timing Closure DFT Unified Power Format Equivalence Checking Assertion Writing State Machines Clock Domain Crossing Mixed-Signal Static Checkers
10+ yrs exp
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DDR Design Engineer

Apple Inc

San Diego, CA 15 days ago $122,700–$214,300
Actively hiring Confirmed live today High trust Below market
Verilog SystemVerilog RTL Design DDR PHY Logic Synthesis Timing Closure Unified Power Format DFT Scan Equivalence Checking Assertion Writing State Machines Clock Domain Crossing Mixed-Signal Silicon Bring-up
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High-Speed HBM, LPDDR Memory Subsystem ASIC Digital Design Engineer

Qualcomm

San Diego, CA 15 days ago $145,600–$218,400
Actively hiring Confirmed live today Trusted Competitive pay
ASIC Design RTL Coding HBM LPDDR DDR NoC SRAM Cache Controller x86 ARM Synthesis Timing Closure Gate Level Simulation Power Analysis Digital Design Hardware Architecture
4+ yrs exp
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High-Speed HBM, LPDDR Memory Controller ASIC Digital Design Engineer

Qualcomm

San Diego, CA 15 days ago $145,600–$218,400
Actively hiring Confirmed live today High trust Competitive pay
ASIC Design RTL Coding Digital Design HBM LPDDR DDR NoC SRAM Cache Controller x86 ARM Gate Level Simulation Synthesis Timing Closure Power Analysis Hardware Architecture
4+ yrs exp
Save

DDR Design Engineer

Apple Inc

Austin, TX 153 days ago
Actively hiring Confirmed live today High trust
Verilog SystemVerilog RTL Design DDR PHY Logic Synthesis Timing Closure Unified Power Format DFT Assertion Writing Clock Domain Crossing State Machines Mixed-Signal Silicon Bring-up
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DDR Design Engineer

Apple Inc

Cupertino, CA 161 days ago $129,300–$225,300
Actively hiring Confirmed live today Trusted Competitive pay
Verilog SystemVerilog RTL Design DDR PHY Logic Synthesis Timing Closure Unified Power Format DFT Scan Assertion Writing State Machines Clock Domain Crossing Equivalence Checking Mixed-Signal Silicon Bring-up
Save