DDR Design Engineer

Apple Inc

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Quick summary

Work type
On-site
Location
Cupertino, CA
Salary
$129,300–$225,300 / yr
Posted
161 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $204k
This role $177k
$116k most similar roles pay here $255k

This role pays less than 56% of similar roles. Most pay $167,175–$241,750 — the shaded band above. At the midpoint, this role pays about $177k versus about $204k for comparable roles.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3513 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2730 roles with salary data.

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At a glance

TL;DR · DDR Design Engineer

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As a DDR Design Engineer, you will join the DDR PHY design team to develop high-performance, low-power designs. You will be involved in all phases of the logic design lifecycle, including concept studies, architecture definition, design, verification, silicon bring-up, and characterization. Your daily responsibilities include performing performance, gate count, and power studies; writing detailed design specifications and test plans; and providing high-quality RTL descriptions with assertions. You will utilize formal tools and static checkers to ensure RTL quality while driving functional coverage and timing closure. The role requires proficiency in Verilog or SystemVerilog, state machines, data paths, arbitration, clock domain crossing logic, and logic synthesis. Additional technical skills include Design For Test, scan concepts, Unified Power Format for simulation and synthesis, and experience within a mixed-signal environment for DDR PHY design.

Skills

Verilog SystemVerilog RTL Design DDR PHY Logic Synthesis Timing Closure Unified Power Format DFT Scan Assertion Writing State Machines Clock Domain Crossing Equivalence Checking Mixed-Signal Silicon Bring-up

What you'll do

  • Perform concept studies to define performance, gate count, and power requirements for digital designs.
  • Write detailed design specifications and test plans in coordination with architecture and verification teams.
  • Develop high-quality RTL descriptions including assertions using Verilog or SystemVerilog.
  • Utilize formal tools and static checkers to ensure high-quality RTL code.
  • Drive functional and code coverage while ensuring timing closure for all designs.
  • Support design verification to ensure bug-free first silicon.
  • Perform silicon bring-up, performance characterization, and power characterization.

What we're looking for

  • Bachelor of Science in Electrical Engineering.
  • RTL design using Verilog or SystemVerilog and assertion writing (preferred).
  • Design of state machines, data paths, arbitration, and clock domain crossing logic (preferred).
  • Logic synthesis and timing constraints (preferred).
  • Exposure to Design For Test and writing DFT friendly RTL (preferred).
  • Unified Power Format for simulation, synthesis, electrical rule checking, and Equivalence checking (preferred).
  • Prior experience in DDR PHY design and mixed-signal environment (preferred).

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