DDR Design Engineer

Apple Inc

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Work type
On-site
Location
Austin, TX
Posted
153 days ago
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Confirmed live today
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99+ roles within 25 mi

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Similar $204k
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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3513 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2730 roles with salary data.

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TL;DR · DDR Design Engineer

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As a DDR Design Engineer, you will join the DDR PHY design team to develop high-performance, low power designs for upcoming products. You will be involved in every phase of the development cycle, including concept study, architecture definition, design, verification, silicon bring-up, and characterization. Your daily responsibilities involve performing concept studies regarding performance, gate count, and power while writing detailed design specifications and test plans alongside circuit designers and verification engineers. You will provide high-quality RTL descriptions using Verilog or SystemVerilog, including assertions, while utilizing formal tools and static checkers to ensure quality. Key technical tasks include managing functional and code coverage, achieving timing closure, and navigating mixed-signal environments. Required skills include experience with state machines, data paths, arbitration, clock domain crossing logic, logic synthesis, Unified Power Format, and Design For Test.

Skills

Verilog SystemVerilog RTL Design DDR PHY Logic Synthesis Timing Closure Unified Power Format DFT Assertion Writing Clock Domain Crossing State Machines Mixed-Signal Silicon Bring-up

What you'll do

  • Perform concept studies to define performance, gate count, and power requirements for digital designs.
  • Write detailed design specifications and test plans in coordination with architecture and verification teams.
  • Develop high-quality RTL descriptions including assertions using Verilog or SystemVerilog.
  • Utilize formal tools and static checkers to ensure high-quality RTL code.
  • Drive functional coverage and achieve timing closure for assigned designs.
  • Support design verification to ensure bug-free first silicon.
  • Assist in silicon bring-up, performance characterization, and power characterization.

What we're looking for

  • Bachelor of Science in Electrical Engineering.
  • RTL design using Verilog or SystemVerilog, including assertion writing (preferred).
  • Experience with design of state machines, data paths, arbitration, and clock domain crossing logic (preferred).
  • Experience with logic synthesis and timing constraints (preferred).
  • Exposure to Design For Test, scan concepts, and writing DFT friendly RTL (preferred).
  • Experience with Unified Power Format for simulation, synthesis, electrical rule checking, and equivalence checking (preferred).
  • Prior experience in DDR PHY design and mixed-signal environment (preferred).

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