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LTspice Spice TI WorkBench Cadence Allegro DxDesigner AC Power Integrity Simulation DC Power Integrity Simulation High efficiency DC-DC power conversion Phase and gain margins Power supply layout Thermal design rules Multi-phase power delivery Ultra-low noise power delivery Power-up sequencing PCB layout techniques Grounding techniques Low noise etch techniques Technical presentation skills +13 more Show less

C/C++ Verilog SystemVerilog CHI ACE Cache coherence protocols Data caches Coherent interconnects Processor architecture Micro-architecture IP development Performance analysis SoC integration System-level performance modeling +9 more Show less

Python SQL Jira Zendesk Salesforce Tableau Google Workspace Microsoft Office CI/CD Kanban Scrum Lean Six Sigma NPS CSAT Trello Confluence AWS Azure GCP +14 more Show less

LTSpice ADS VxDesigner Allegro PCB SiP Layout Python Power Integrity simulations optical components digital control loops DSP functions transmission line theory high-efficiency DC-DC power converters analog/RF simulation tools PCB layout and constraint management +9 more Show less

C# Python C++ Bugzilla Jira

Redis Memcached Java Python C++ AI CI/CD Docker Kubernetes AWS PostgreSQL Prometheus Grafana Git Jenkins +10 more Show less

Python C++ Matlab VPI JMP PAM4 coherent_optical_communications RF_EO_OE_testing client_optics_DSP_SerDes_testing DAC_ADC_operations test_automation data_analysis_software software_and_testAutomation +8 more Show less

SystemVerilog UVM C++ Python Perl TCL DSP algorithms QAM Formal Verification Jasper VCFormal CI/CD Git Linux +9 more Show less

SystemVerilog UVM C++ Jasper VCFormal Python Perl TCL Makefile Git CI/CD Docker AWS Kubernetes +9 more Show less

C++ C RTOS ARM processors Perforce GIT Bugzilla JIRA Jira Crucible Python make shell programming +7 more Show less

LTSpice ADS VxDesigner Allegro PCB SiP Layout Python Power Integrity simulations optical components digital control loops DSP functions +5 more Show less

C++ C RTOS ARM Python Git Perforce JIRA Bugzilla Crucible UNIX Make Shell programming +8 more Show less

AWS gRPC Kubernetes Python Kotlin MySQL Java Snowflake CI/CD Domain-Driven Design Docker Prometheus Grafana Sentry.io Rollbar Chronosphere Kibana +12 more Show less

AWS gRPC Kubernetes Python Snowflake Kotlin MySQL Java Sentry.io Rollbar Chronosphere Kibana +7 more Show less

RTL Cache PPA ASIC Memory_Systems Multi_Processor_Coherence_Protocols DRAM_Controller SoC Register_Transfer_Level Front_End_Netlist_Analysis Physical_Design_Timing_Closure +6 more Show less

RTL Verilog SystemVerilog Cache Coherence Protocols DRAM Controller PPA Analysis SoC Design ASIC Design Memory Systems High Performance Computing Mentor Graphics Calibre Synopsys DC Compiler Tensilica Diamond Standard Library +8 more Show less

Verilog RTL ASIC Synthesis Timing_Analysis Floor_Planning DFT ECO Cache_Coherency High_Speed_Interconnects Computer_Architecture +6 more Show less