ASIC Design Engineer - Cache Controller

Apple Inc

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $181,100–$318,400 / yr
Posted: 52 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $193k

This role $250k

$133k most similar roles pay here $338k

This role pays more than 91% of similar roles. Most pay $169,625–$216,250 — the shaded band above. At the midpoint, this role pays about $250k versus about $193k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1723 open roles on FindRole.

Listed pay typically runs $162,500–$272,100 across 1398 roles with salary data.

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At a glance

TL;DR · ASIC Design Engineer - Cache Controller

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As an ASIC Design Engineer specializing in cache controllers at Apple, you will join the cutting-edge hardware team responsible for developing the world’s fastest mobile processing systems. Your primary focus will be on designing and implementing high-performance cache subsystems within SoCs, including defining micro-architectures based on architectural guidelines and conducting performance analysis to optimize system PPA (performance, power, area). You will develop RTL designs, collaborate with physical design teams for timing closure, and work closely with multi-client memory systems that demand real-time, low-latency, and high-bandwidth capabilities. Essential skills include extensive ASIC design experience, cache micro-architecture definition, and hands-on knowledge of multi-processor cache coherence protocols. Preferred qualifications involve expertise in high-performance coherent memory systems or interconnect architectures and DRAM controllers.

Skills

RTL Cache PPA ASIC Memory_Systems Multi_Processor_Coherence_Protocols DRAM_Controller SoC Register_Transfer_Level Front_End_Netlist_Analysis Physical_Design_Timing_Closure

What you'll do

Design and develop hardware for cache subsystems in high-performance SoCs.
Develop cache micro-architecture based on architecture guidelines and model analysis.
Explore performance, area, and power consumption trade-offs in system design.
Debug register-transfer level (RTL) designs of various sections in the cache subsystem.
Conduct front-end netlist and area/timing analysis for the cache subsystem.
Collaborate with physical design team to achieve timing closure for the cache subsystem.

What we're looking for

10+ years of full-time ASIC design experience
Expertise in cache micro-architecture and RTL development
Proficiency in PPA analysis for system optimization
Hands-on experience with multi-processor cache coherence protocols
Background in memory systems, including various memory organizations
Knowledge of high-performance coherent memory systems or interconnect architectures

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