ASIC Design Engineer - Cache Controller

Apple Inc

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $147,400–$272,100 / yr
Posted: 52 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $193k

This role $210k

$132k most similar roles pay here $287k

This role pays more than 69% of similar roles. Most pay $169,625–$216,250 — the shaded band above. At the midpoint, this role pays about $210k versus about $193k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1723 open roles on FindRole.

Listed pay typically runs $162,500–$272,100 across 1398 roles with salary data.

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At a glance

TL;DR · ASIC Design Engineer - Cache Controller

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As an ASIC Design Engineer specializing in Cache Controller at Apple, you will join the cutting-edge hardware team responsible for developing the world’s fastest mobile processing systems. Your primary responsibilities include designing and implementing cache subsystems within high-performance SoCs, exploring architecture trade-offs to optimize system performance, area, and power consumption, and developing RTL designs for various sections of the cache subsystem. You will collaborate closely with physical design teams on timing closure and front-end netlist analysis. The ideal candidate has a strong background in memory system development, experience with multi-processor cache coherence protocols, and knowledge of high-performance coherent memory systems or interconnect architectures. This role demands expertise in RTL/micro-architecture definition, PPA analysis, and familiarity with advanced memory organizations and trade-offs.

Skills

RTL Verilog SystemVerilog Cache Coherence Protocols DRAM Controller PPA Analysis SoC Design ASIC Design Memory Systems High Performance Computing Mentor Graphics Calibre Synopsys DC Compiler Tensilica Diamond Standard Library

What you'll do

Design and develop hardware for cache subsystems in high-performance SoCs.
Develop cache micro-architecture based on architecture guidelines and model analysis.
Explore performance, area, and power consumption trade-offs in system design.
Debug register-transfer level (RTL) designs of various sections in the cache subsystem.
Conduct front-end netlist and area/timing analysis for the cache subsystem.
Collaborate with physical design teams to achieve timing closure for cache subsystems.

What we're looking for

3+ years of full-time ASIC design experience
Expertise in RTL/micro-architecture definition and PPA analysis
Background in cache design, including memory organizations and trade-offs
Experience with multi-processor cache coherence protocols
Knowledge of high-performance coherent memory systems or interconnect architectures

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