ASIC Design Engineer, Cache Controller

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $150,400–$277,600 / yr
Posted: 144 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $202k

This role $214k

$135k most similar roles pay here $293k

This role pays more than 66% of similar roles. Most pay $176,200–$227,300 — the shaded band above. At the midpoint, this role pays about $214k versus about $202k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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At a glance

TL;DR · ASIC Design Engineer, Cache Controller

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As an ASIC Design Engineer - Cache Controller, you will join the team responsible for developing hardware for the cache subsystem within high-performance systems on a chip. Your daily responsibilities include developing cache micro-architecture based on model analysis and architecture guidelines while exploring critical trade-offs regarding system performance, area, and power consumption. You will develop and debug register-transfer level design for various sections of the cache subsystem, perform front-end netlist and area/timing analysis, and collaborate with physical design teams to achieve timing closure. The role requires expertise in RTL, micro-architecture definition, PPA analysis, and memory system development. You will address complex challenges in high-bandwidth multi-client memory subsystems, specifically focusing on the technical requirements of coherent memory systems, interconnect architectures, and high-performance DRAM controllers within a sophisticated SoC memory hierarchy.

What does a ASIC Design Engineer earn in California?

Median $214000 from 47 postings across 8 companies.

See salary data

Skills

ASIC Design RTL Micro-architecture SoC Cache Coherence DRAM Controller Timing Closure Netlist Memory Systems Interconnect Architectures

What you'll do

Design and develop hardware for the cache subsystem in high-performance systems on a chip (SoC).
Develop cache micro-architecture based on architectural guidelines and model analysis.
Analyze architecture trade-offs regarding system performance, area, and power consumption.
Develop and debug register-transfer level (RTL) designs for various sections of the cache subsystem.
Perform front-end netlist, area, and timing analysis for the cache subsystem.
Coordinate with the physical design team to achieve timing closure for the cache subsystem.

What we're looking for

Bachelor of Science in a relevant field.
Master of Science in a relevant field is preferred.
At least 3 years of full-time ASIC design experience.
Experience in memory system development and RTL/micro-architecture definition.
Proficiency in PPA (performance, power, area) analysis.
Background in cache design with an understanding of memory organizations and tradeoffs.
Experience with multi-processor cache coherence protocols.
Knowledge of high-performance coherent memory systems, interconnect architectures, or DRAM controllers.