Senior Logic Design Engineer, Cache Coherent Interconnects

Nvidia

Quick summary

Work type
On-site
Location
Santa Clara, CA · Hillsboro, OR
Salary
$136,000–$218,500 / yr
Posted
80 days ago

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Competitive pay

How this pay compares to similar roles

Similar $196k
This role $177k
$125k most similar roles pay here $242k

This role pays less than 58% of similar roles. Most pay $170,750–$222,000 — the shaded band above. At the midpoint, this role pays about $177k versus about $196k for comparable roles.

Based on 240 similar postings.

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About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 563 open roles on FindRole.

Listed pay typically runs $168,000–$264,500 across 556 roles with salary data.

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At a glance

TL;DR · Senior Logic Design Engineer, Cache Coherent Interconnects

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As a Senior Logic Design Engineer on our CPU Logic Design Team, you will play a pivotal role in designing high-performance CPU interconnect networks, coherency protocols, and last-level caches. Your daily responsibilities include defining micro-architectures, writing efficient RTL code, debugging logic issues, ensuring synthesis and timing closure, and collaborating with verification teams to validate your designs. You will also work closely with implementation teams to optimize performance, power consumption, and area efficiency while mentoring junior engineers. This role requires expertise in Verilog, a deep understanding of the ASIC design flow, and experience in processor or high-performance semiconductor design. Ideal candidates have a Master’s Degree in Electrical Engineering, Computer Engineering, or Computer Science, along with 5+ years of relevant industry experience and a strong background in computer architecture, cache coherency, and high-speed interconnects.

Skills

Verilog RTL ASIC Logic Synthesis DFT Timing Analysis Floor-planning ECO Cache Coherency High Speed Interconnects Computer Architecture

What you'll do

  • Design and deliver high-performance, low-power RTL code for CPU interconnects and caches.
  • Ensure synthesis and timing closure for assigned units on the chip.
  • Collaborate with verification teams to validate design correctness.
  • Mentor junior engineers and provide guidance in logic design and verification.
  • Assist implementation team to meet performance, power, and area goals.
  • Document design processes and contribute to overall project documentation.

What we're looking for

  • Master’s Degree in Electrical Engineering, Computer Engineering or Computer Science required.
  • 5+ years of experience in processor or related high performance semiconductor designs.
  • Expertise in Verilog and deep understanding of ASIC design flow including RTL design and verification.
  • Strong communication skills for working effectively in a dynamic global team environment.
  • Experience with logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.
  • Background in computer architecture, cache coherency or high speed interconnects preferred.

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