Senior Logic Design Engineer, Cache Coherent Interconnects

Nvidia

Confirmed live yesterday Trusted

Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CAHillsboro, OR
Salary: $136,000–$218,500 / yr
Posted: 177 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

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Competitive pay

How this pay compares to similar roles

Similar $196k

This role $177k

$125k most similar roles pay here $241k

This role pays less than 60% of similar roles. Most pay $175,000–$216,250 — the shaded band above. At the midpoint, this role pays about $177k versus about $196k for comparable roles.

Based on 240 similar postings.

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About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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At a glance

TL;DR · Senior Logic Design Engineer, Cache Coherent Interconnects

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As a Senior Logic Design Engineer, Cache Coherent Interconnects, you will join the CPU Logic Design Team to design on-chip and off-chip interconnect networks, MP coherency, and last-level and system caches. Your daily responsibilities include micro-architectural definition, writing high-performance and low-power RTL, logic debug, synthesis, timing closure, and creating design documentation. You will collaborate with verification teams to ensure unit correctness while working with implementation teams to meet specific area, performance, and power goals. The role requires expertise in Verilog and a deep understanding of the ASIC design flow, including prototyping, DFT, floor-planning, ECO, and lab debug. Candidates should possess a strong background in computer architecture, cache coherency, or high-speed interconnects. This position focuses on solving complex technical challenges within processor and high-performance semiconductor designs for advanced computing platforms.

Skills

Verilog RTL ASIC Design Flow Logic Synthesis Timing Closure Computer Architecture Cache Coherency high speed interconnects DFT Floor-planning ECO Lab Debug

What you'll do

Design on-chip and off-chip interconnect networks, MP coherency, and system caches.
Define micro-architectures for specific CPU units.
Write high-performance and low-power RTL code.
Perform logic synthesis and achieve timing closure for super units.
Create comprehensive design documentation for assigned components.
Partner with the verification team to ensure unit correctness.
Work with implementation teams to meet area, performance, and power goals.

What we're looking for

Master’s Degree in Electrical Engineering, Computer Engineering, or Computer Science (or equivalent experience).
5+ years of experience in processor or related high-performance semiconductor designs.
Expertise in Verilog and RTL coding for high performance and low power.
Deep understanding of ASIC design flow including synthesis, timing analysis, floor-planning, and lab debug.
Strong background in computer architecture, cache coherency, or high-speed interconnects.
Strong communication and interpersonal skills to work within a dynamic, global team.
Proven track record of mentoring junior engineers and interns is preferred.

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