Senior Logic Design Engineer, Cache Coherent Interconnects

Nvidia

Confirmed live today High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Santa Clara, CAHillsboro, OR
Salary
$136,000–$218,500 / yr
Employment
Full-time
Posted
5 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

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Competitive pay

How this pay compares to similar roles

Similar $198k
This role $177k
$123k $258k
below market most similar roles pay here above market

This role pays less than 63% of similar roles. Most pay $173,950–$223,000 — the blue band above. At the midpoint, this role pays about $177k versus about $198k for comparable roles.

Based on 240 similar postings.

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About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1792 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1179 roles with salary data.

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At a glance

TL;DR · Senior Logic Design Engineer, Cache Coherent Interconnects

Role Posting Log in to save

As a Senior Logic Design Engineer, Cache Coherent Interconnects, you will join the CPU Logic Design Team to own the design and timely delivery of specific chip units. Your daily responsibilities include writing high-performance, low-power RTL, performing logic debug, and managing synthesis and timing closure. You will also produce design documentation and collaborate with verification and implementation teams to meet area, performance, and power goals. The role requires expertise in Verilog and a deep understanding of the ASIC design flow, including RTL design, prototyping, DFT, timing analysis, floor-planning, and ECO. You will work on critical hardware components including CPU on-chip and off-chip interconnect networks, MP coherency, and last-level and system caches to solve complex problems in high-performance semiconductor design.

Skills

Verilog RTL Design ASIC Design Flow Logic Synthesis Timing Closure DFT Timing Analysis Floor-planning ECO Computer Architecture Cache Coherency Logic Debug Prototyping Bring-up Lab Debug

What you'll do

  • Design CPU on-chip and off-chip interconnect networks, MP coherency, and system caches.
  • Define micro-architectures and write high-performance, low-power RTL code.
  • Perform logic synthesis and ensure timing closure for specific chip units.
  • Create comprehensive design documentation for assigned hardware units.
  • Partner with the verification team to ensure the functional correctness of designs.
  • Work with the implementation team to meet area, performance, and power goals.
  • Assist with timing closure for larger super units.

What we're looking for

  • Master’s Degree in Electrical Engineering, Computer Engineering, or Computer Science or equivalent experience.
  • 5+ years of experience in processor or other related high performance semiconductor designs.
  • Expertise in Verilog and a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, and timing analysis.
  • Experience with prototyping, DFT, floor-planning, ECO, bring-up, and lab debug.
  • Strong communication and interpersonal skills for working in a dynamic, global team.
  • Successful track record of mentoring junior engineers and interns (preferred).
  • Strong background in computer architecture, cache coherency, or high speed interconnects (preferred).

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