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Staff Engineer, ASIC Design Verification

Samsung Semiconductor

San Jose, CA today $163,000–$253,000
Actively hiring Posted today Verified listing Competitive pay
UVM C++ SystemVerilog ASIC verification UCIe HBM controller Memory DFT DDR Custom HBM CI/CD
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ASIC Verification Engineer

Snap Inc.

Santa Monica, CA 1 day ago
Actively hiring Posted today Verified listing
UVM SystemVerilog constraint-random verification coverage-driven sign-off Artificial Intelligence tools NPUs image/video processing pipelines custom silicon architectures Synopsys front-end suites MIPI RTL VHDL CI/CD Git
Hybrid
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ASIC Design Verification Engineer

Cisco

Remote (San Jose, CA) 2 days ago $123,600–$174,000
Actively hiring Posted this week Verified listing Below market
SystemVerilog UVM Perl Python Veloce Palladium Zebu HAPS IEV VC Formal PCIe CXL Ethernet RDMA DDR TCP
Remote
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ASIC Design Verification Engineering Technical Leader

Cisco

Remote (San Jose, CA) 9 days ago $183,800–$263,600
Actively hiring Verified listing Above market
SystemVerilog UVM Linux C++ Python Perl Veloce Palladium Zebu HAPS CI/CD Networking Dashboard_management Emulation_platforms
Remote
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Senior ASIC Design Verification Engineer

Nvidia

Santa Clara, CA 15 days ago $136,000–$218,500
Actively hiring Verified listing Competitive pay
Verilog SystemVerilog UVM SVA VCS Perl Tcl Makefiles Python LLMs Agentic AI frameworks VCS-XA Gate Level Simulation Formal Equivalence
Hybrid
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ASICS Design Verification Engineer

Qualcomm

San Diego, CA 15 days ago $115,600–$173,400
Actively hiring Below market
SystemVerilog UVM SystemVerilog-UVM C++ C Perl Python VHDL Verilog AMBA_Bus_Protocol Formal_Verification Assertion_Based_Formal_Verification
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