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Active Keyword: ASIC DFT Engineer Remove filter Clear all

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Sr. ASIC DFT Engineer (Silicon)

SpaceX

Irvine, CA 2 days ago $125,000–$150,000
Actively hiring Posted this week Verified listing Below market
Siemens_Tessent Perl Python Tcl C++ IEEE_1500 IEEE_1687 In-System_Test_(IST) boundary_scan_IEEE_1149_1 Automated_Test_Equipment_(ATE) Teradyne Advantest Streaming_Scan_Network cell-aware_fault_models_ATPG
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ASIC Engineering Technical Lead - DFT

Cisco

San Jose, CA 38 days ago $183,800–$263,600
Actively hiring Above market
Python Tcl C++ Siemens_Tessent Synopsys RTL Verilog System_Verilog DFT ATPG SDF Scan_Insertion Memory_BIST Logic_BIST ATE_testers
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ASIC DFT Engineer

Broadcom

San Jose, CA 39 days ago $141,300–$226,000
Actively hiring Verified listing Competitive pay
TetraMax Fastscan Verilog IEEE1687 IJTAG ICL PDL Python Statistical_Process_Control ATE Serdes DDR PCIE ENET CXL I/O_BIST DFT Testbench_Generation Simulation Debugging Root_Cause_Analysis
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ASIC DFT Engineer

Broadcom

San Jose, CA 40 days ago $141,300–$226,000
Actively hiring Verified listing Competitive pay
DFT Scan MBIST TAP LBIST IO SerDes Pattern_Generation ATPG TetraMax Fastscan Verilog IEEE1149.1 IEEE1149.6 TestKompress Mentor_TestKompress Boundary_Scan IEEE1687 IJTAG ICL PDL Test-STA Analog_Design Digital_Circuit_Design Si_Processing Logical_Synthesis Physical_Synthesis Statistical_Process_Control ATE DDR PCIE ENET CXL_IOBIST Tessent_SSN
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ASIC DFT Engineer

Broadcom

Fort Collins, CO 106 days ago $108,000–$172,800
Actively hiring Verified listing Below market
TCL PERL RUBY Python C++ Verilog IEEE1687 IJTAG ICL PDL TetraMax Fastscan ATE Serdes DDR PCIE ENET CXL I/O BIST Statistical Process Control
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ASIC DFT Engineer

Broadcom

Fort Collins, CO 106 days ago $108,000–$172,800
Actively hiring Verified listing Below market
TCL PERL RUBY Python C++ Verilog IEEE1687 IJTAG ICL PDL TetraMax Fastscan ATE Serdes DDR PCIE ENET CXL I/O BIST Statistical Process Control
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