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Active Keyword: ASIC DFT Engineer Remove filter Clear all

6 of up to 20 (filtered)

ASIC DFT Engineer

Broadcom

San Jose, CA 17 days ago
Actively hiring Confirmed live 2 days ago High trust
DFT ATPG Scan Insertion MBIST TAP LBIST Verilog Tessent SSN Mentor TestKompress TetraMax Fastscan IEEE1149.1 IEEE1149.6 IEE1687 IJTAG ICL PDL STA SerDes DDR PCIe
10+ yrs exp
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ASIC/SOC DFT Engineer

SpaceX

Austin, TX 36 days ago
Actively hiring Confirmed live yesterday Low trust
ASIC DFT Scan Insertion ATPG Verilog SystemVerilog Python Bash Perl UPF Gate Level Simulation SDF RTL Physical Design Formal Verification DRC Synthesis Silicon Engineering
1+ yrs exp
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ASIC/SOC DFT Engineer

SpaceX

Palo Alto, CA 36 days ago $135,000–$175,000
Actively hiring Confirmed live yesterday Trusted Below market
ASIC DFT Scan Insertion ATPG Verilog SystemVerilog Python Bash Perl UPF Gate Level Simulation SDF DRC Formal Verification RTL Physical Design
1+ yrs exp
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Senior ASIC DFT Engineer

SpaceX

Austin, TX 105 days ago
Actively hiring Confirmed live yesterday Low trust
DFT Siemens Tessent ATPG Scan Insertion Memory BIST Logic BIST Python Perl Tcl C++ ATE Teradyne Advantest SDF IEEE 1500 IEEE 1149.1 Boundary Scan Post-Silicon Validation
5+ yrs exp
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Senior ASIC DFT Engineer

SpaceX

Irvine, CA 105 days ago $165,000–$260,000
Actively hiring Confirmed live yesterday Low trust Competitive pay
DFT Siemens Tessent ATPG Python Perl Tcl C++ Gate-level Simulation SDF ATE Teradyn Advantest IEEE 1500 IEEE 1149.1 BIST Scan Insertion Post-silicon Validation
5+ yrs exp
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Senior ASIC DFT Engineer

SpaceX

Palo Alto, CA 105 days ago $175,000–$280,000
Actively hiring Confirmed live 2 days ago Low trust Above market
DFT Siemens Tessent ATPG Python Perl Tcl C++ Gate-level Simulation SDF ATE Teradyn Advantest IEEE 1500 IEEE 1149.1 BIST Scan Insertion Post-silicon Validation
5+ yrs exp
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