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SoC Architecture SystemVerilog Verilog VHDL AMBA Synthesis Formal Verification CDC DFT Timing Closure Git JIRA DRAM SERDES UART Design Validation +11 more Show less

Agile/Scrum Jira Confluence SQL Python AWS Azure GCP SDLC CI/CD REST/GraphQL Git/GitHub Docker Kubernetes Power BI Tableau Salesforce HubSpot Google Analytics Figma Adobe Creative Suite HTML/CSS Java C++ Linux Microsoft Excel Microsoft Project Smartsheet A/B testing +24 more Show less

C++ SystemVerilog Verilog HDL Python Perl Ruby x86 Assembly Computer Architecture ASIC SoC Formal Verification Simulation DFT RTL Tape-out +10 more Show less

RTL Design Microarchitecture Verilog SystemVerilog HDL Cache Architecture CPU Coherency SoC Chiplet Lint CDC RDC Scripting Low-Power Design RAS ECC Tapeout Physical Design Design For Test +14 more Show less

Solidworks Ansys Icepack Ansys Mechanical Python Excel Allegro Thermal Management PCB Design Simulations Profilometry Keyence ATE Test Hardware Mechanical Prototyping +8 more Show less

AI ML Optimization Applied Probability Software Development JIRA Confluence GitHub Simulation Frameworks Estimation Engines C2 system. + S Release Management +7 more Show less

Package Design ASIC SerDes HBM DDR5 Signal Integrity Power Integrity DFx Thermal Modeling Automation Project Management Layout Simulations RF Microwave ADC DAC +12 more Show less

C++ Verilog HDL Digital RTL Design Computer Architecture SoC Performance Modeling Performance Analysis Simulators Emulation Post-silicon Observation Scripting Hardware Design Microarchitecture +8 more Show less

C++ Verilog HDL Digital RTL Design Computer Architecture SoC Performance Modeling Performance Analysis Emulation Post-silicon Observation Scripting Hardware Design Microarchitecture +7 more Show less

Salesforce Financial Services Cloud OmniStudio Salesforce Marketing Cloud Apex Lightning Web Components Flow MuleSoft REST SOAP Data Cloud Agentforce Experience Cloud Copado Jira Confluence Journey Builder DataRaptors FlexCards OmniScripts +14 more Show less

Infrastructure-as-Code Ansible DevSecOps CI/CD AWS GCP Azure Firewalls VPN Zero-Trust Architecture Virtualization Incident Response Threat Modeling VPC Design Monitoring Logging Detection Engineering Agile +13 more Show less

UVM System Verilog Python Shell Pearl Git ASIC FPGA IP Verification Silicon Chip Architecture Performance Instrumentation +6 more Show less

ASIC Design IC Design Floor Planning Routing Timing Analysis Physical Verification Signal Integrity Power Integrity SerDes CMOS Clocking Structures +6 more Show less

ASIC Design Physical Design VLSI Place&Route Verilog DRC LVS STA Tcl Perl Python UNIX Linux DSP EDA Tools +10 more Show less

Product Operations Portfolio Management Product Strategy Product Discovery Systems Thinking Customer Research Hardware Software Business Metrics +4 more Show less

ASIC Design IC Design Floor Planning Routing Timing Analysis Physical Verification SerDes Signal Integrity Power Integrity CMOS Clocking Structures +6 more Show less

Firmware Windows Linux Platform Software Root-Cause Analysis Hardware Enablement Driver Integration RSC Technical Program Management Automation High-Performance Computing Enterprise Deployment +7 more Show less

IC Package Design Flip-chip BGA ASIC SerDes Signal Integrity Power Integrity HBM DDR5 Cadence APD Allegro Package Designer Cadence SKILL Physical Design Layout RF Microwave ADC DAC +12 more Show less

Place and Route Timing Closure STA Floor-planning Clock Tree Synthesis Physical Verification LVS DRC Equivalence Checks Power Optimization ECO ICC2 Innovus Primetime Caliber LEC SoC Design +12 more Show less

Python Java Go C++ REST APIs HTTP OAuth 2.0 OpenID Connect SSO TLS Microsoft Entra Azure AD IAM LLM APIs GitHub Copilot Agile +11 more Show less