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C C++ Python Verilog SystemVerilog Perl Matlab Vulkan UVM RTL ASIC SoC DSP LTE 5G Wi-Fi Linux Windows Machine Learning +14 more Show less

Physical Verification DRC LVS ERC Calibre P&R Flows Floorplanning GPU Architecture Design for Yield Manufacturability ESD Multi Vt Strategies Global Timing Verification +8 more Show less

ASIC Implementation Physical Design Place and Route PPA Optimization Synthesis DFT Floorplanning TCL Perl Python RTL Power Distribution Physical Signoff Design for Yield Thermal Management multi Vt +11 more Show less

ASIC Integration Physical Design Clock Distribution Floorplanning P&R Flows Timing Verification Netlist to Tapeout PPA ESD Solutions Design for Yield Manufacturability multi Vt strategies GPU Architecture +8 more Show less

Physical Design ASIC Implementation Place and Route Floorplanning Synthesis DFT Clock and Power Distribution RTL Multi-voltage Power Retention Design for Yield Manufacturability Thermal Management +8 more Show less

SystemVerilog UVM Verilog VHDL RTL Verification Computer Architecture Perl Ruby Shell Scripting Makefiles Graphics Pipeline Functional Coverage Simulations Waveform Viewers +9 more Show less

SystemVerilog UVM Verilog VHDL RTL Verification GPU Architecture Graphics Pipeline Perl Ruby Shell Scripting Makefiles HDL Simulators Waveform Viewers Functional Coverage +9 more Show less

SystemVerilog Verilog RTL Verification Computer Architecture GPU Architecture Object Oriented Programming Data Structures Perl Ruby Shell Scripting Makefiles HDL Simulators Waveform Viewers SoC +9 more Show less

Verilog System Verilog HDL Python Perl Ruby GPU Architecture SoC RTL Coding Cache On-chip Interconnect Data Compression Power Optimization Functional Simulation Debug +10 more Show less

GPU Architecture Micro-architecture Verilog System Verilog HDL RTL C++ Python Perl Ruby SoC Cache Memory Subsystem On-chip Interconnect Data Compression Architectural Modeling +11 more Show less

ASIC Integration Physical Design Floorplanning Place and Route RTL Clock and Power Distribution Global Signal Planning I/O Planning Cadence Synopsys Timing Verification Physical Design Verification Design for Yield Manufacturability multi Vt strategies +10 more Show less

ASIC Integration Physical Design Floorplanning Place and Route P&R Flows Timing Verification Physical Design Verification Clock and Power Distribution Global Signal Planning I/O Planning Hard IP Integration Mixed Signal Block Integration Design for Yield Manufacturability Multi Vt Strategies RTL Netlist to Tapeout +12 more Show less

ASIC Implementation Physical Design Place and Route Floorplanning Synthesis DFT Clock and Power Distribution RTL Multi-voltage Power Retention Design for Yield Manufacturability Thermal Management Hierarchical Design Top-down Design +10 more Show less

System Verilog UVM C/C++ Verilog VHDL Python Vulkan Make Airflow Veloce Palladium Zebu FPGA QEMU GDB Formal Verification Emulation Prototyping +13 more Show less

ASIC SystemVerilog Verilog UVM Python Perl VCS Verdi Xcelium RTL Pre-silicon Verification infrastructure, automation Simulation Debug Root-cause Analysis +10 more Show less

ASIC Implementation Physical Design Place and Route Synthesis DFT Floorplanning TCL Perl Python PPA Optimization RTL Power Distribution Physical Signoff Design for Yield Thermal Management multi Vt +11 more Show less