Browse tech roles

Basic role filtering by workplace, salary floor, and post age. For full AI matching and advanced filtering upload your resume using AI Match.

Active Keyword: ASIC Design Engineer Remove filter Location: San Jose Remove filter Clear all

13 of up to 20 (filtered)

Senior ASIC Design Verification Engineer

Cisco

San Jose, CA 6 days ago $167,700–$245,200
Actively hiring Confirmed live today Posted this week High trust Competitive pay
ASIC Design Verification System Verilog UVM Python Perl Gate Level Simulation Emulation Formal Verification PCIe CXL Ethernet RDMA DDR TCP P4 Veloce Palladium Zebu HAPS OOP
7+ yrs exp
Save

ASIC Package Design Engineer

Broadcom

San Jose, CA +2 8 days ago $143,800–$230,000
Actively hiring Confirmed live yesterday High trust Competitive pay
IC Package Design Flip-chip BGA ASIC SerDes Signal Integrity Power Integrity HBM DDR5 Cadence APD Allegro Package Designer Cadence SKILL Physical Design Layout RF Microwave ADC DAC
10+ yrs exp
Save

ASIC Design Verification Engineer

Cisco

San Jose, CA 11 days ago $155,000–$222,600
Actively hiring Confirmed live today Trusted Competitive pay
System Verilog UVM Python Perl ASIC Gate Level Simulation Veloce Palladium Zebu HAPS P4 PCIe CXL Ethernet RDMA DDR TCP Formal Verification
5+ yrs exp
Save

ASIC Design Verification Engineer

Cisco

San Jose, CA 13 days ago $155,000–$222,600
Actively hiring Confirmed live yesterday High trust Competitive pay
System Verilog UVM Python Perl ASIC Design Verification Gate Level Simulation Veloce Palladium Zebu HAPS VC Formal IEV P4 PCIe CXL Ethernet RDMA DDR TCP
5+ yrs exp
Save

ASIC Design Engineer

Broadcom

San Jose, CA +1 14 days ago $143,800–$230,000
Actively hiring Confirmed live yesterday High trust Competitive pay
ASIC Implementation Synthesis Design for Test Floorplanning Place and Route Clock Methodology Power Planning Timing Closure Signal Integrity Physical Design Checks
10+ yrs exp
Save

ASIC Design Engineer

Broadcom

Irvine, CA +2 14 days ago $121,900–$195,000
Actively hiring Confirmed live today High trust Below market
ASIC Design RTL Design Ethernet PCIe Python Perl Simulation Verification Synthesis Timing Closure Silicon Validation Architecture Definition high speed communication front end design
8+ yrs exp
Save

ASIC Physical Design Engineer

Cisco

San Jose, CA +2 19 days ago
Actively hiring Confirmed live yesterday High trust
RTL-to-GDSII Physical Design Static Timing Analysis STA Innovus Tempus Primetime Redhawk Voltus Calibre Python TCL Perl Clock Tree Synthesis CTS Power Integrity Floorplanning Place and Route Equivalence Checks
6+ yrs exp
Save

ASIC Physical Design Engineer II

Cisco

San Jose, CA 26 days ago $125,700–$203,100
Actively hiring Confirmed live today High trust Below market
ASIC Physical Design RTL-to-GDSII Floor Planning Place and Route Clock Tree Synthesis Static Timing Analysis STA PrimeTime Cadence Innovus Synopsys ICC2 Synopsys Design Compiler Mentor Calibre DRC LVS Python Tcl Perl Logic Synthesis Timing ECO
2+ yrs exp Hybrid
Save

Senior Staff ASIC Design Engineer

Amd

San Jose, CA 53 days ago $200,000–$300,000
Actively hiring Confirmed live today High trust Above market
Verilog System Verilog UVM Python Tcl Perl Shell RTL Design DFT Static Timing Analysis Synthesis place-and-route FPGA PCIe Serdes HBM Synopsys DC Compiler Primetime VCS Cadence Virtuoso
Save

AI-Driven ASIC Physical Design Principal Engineer

Cisco

San Jose, CA 64 days ago
Actively hiring Confirmed live today High trust
Python ASIC EDA Tools Innovus ICC2 Calibre Tcl Docker RAG LLM Pinecone Weaviate OpenAI API GPT-4o MLPD RTL2GDSII Tempus Primetime Redhawk Voltus Pegasus
10+ yrs exp Hybrid
Save

Senior ASIC Design Engineer

Cisco

San Jose, CA 75 days ago
Actively hiring Confirmed live yesterday Trusted
Verilog System Verilog ASIC Design RTL Timing Closure Clock Gating Post Silicon Validation Scripting Micro-architecture Place-and-Route Functional Coverage
7+ yrs exp
Save

ASIC Design Engineer Technical Lead

Cisco

San Jose, CA 91 days ago $186,900–$267,700
Actively hiring Confirmed live yesterday Low trust Above market
ASIC Design Verilog System Verilog Python Perl TCL Shell Programming RTL Micro-architecture Tape-out post silicon validation Simulation
8+ yrs exp
Save

Lead ASIC Design Engineer

Broadcom

San Jose, CA 130 days ago $143,800–$230,000
Actively hiring Confirmed live today High trust Competitive pay
SystemVerilog Verilog RTL Design ASIC SoC Logic Synthesis Static Timing Analysis CDC DFT Python Tcl Perl Design Compiler Genus PrimeTime Tempus SpyGlass JasperGold SDC Mixed-Signal SerDes PCIe DDR
10+ yrs exp
Save